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1
CN112567512A
半导体结构及其形成方法
Substantial Examination
Publication/Patent Number: CN112567512A Publication Date: 2021-03-26 Application Number: 201880096617.4 Filing Date: 2018-06-29 Inventor: 王新胜   张莉   张高升   万先进   华子群   王家文   丁滔滔   朱宏斌   程卫华   杨士宁   Assignee: 长江存储科技有限责任公司   IPC: H01L23/532 Abstract: 本发明涉及一种半导体结构及其形成方法,所述半导体结构包括:第一基底;位于所述第一基底表面的第一粘附层;位于所述第一粘附层表面的第一键合层,所述第一粘附层的致密度大于所述第一键合层的致密度。所述半导体结构的第一粘附层与所述第一基底以及第一键合层之间具有较高的粘附性,有利于提高半导体结构的性能。
2
CN112567511A
半导体结构及其形成方法
Substantial Examination
Publication/Patent Number: CN112567511A Publication Date: 2021-03-26 Application Number: 201880096616.X Filing Date: 2018-06-29 Inventor: 王新胜   张莉   张高升   万先进   华子群   王家文   丁滔滔   朱宏斌   程卫华   杨士宁   Assignee: 长江存储科技有限责任公司   IPC: H01L23/532 Abstract: 本发明涉及一种半导体结构及其形成方法,所述半导体结构包括:第一基底;位于所述第一基底表面的第一键合层,所述第一键合层的材料为包含C元素的介质材料,所述第一键合层背向所述第一基底的表层的C原子浓度大于或等于35%。所述半导体结构在的第一键合层在键合时能够提高键合强度。
3
US2021050301A1
APPARATUS COMPRISING ALUMINUM INTERCONNECTIONS, MEMORY DEVICES COMPRISING INTERCONNECTIONS, AND RELATED METHODS
Publication/Patent Number: US2021050301A1 Publication Date: 2021-02-18 Application Number: 16/539,437 Filing Date: 2019-08-13 Inventor: Sugioka, Shigeru   Fujiki, Noriaki   Kawakita, Keizo   Ishino, Takahisa   Assignee: Micron Technology, Inc.   IPC: H01L23/532 Abstract: An apparatus comprising a multilevel wiring structure comprising aluminum interconnections. The aluminum interconnections comprise a first portion, a second portion, and a third portion, where the second portion is between the first portion and the third portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. A memory device comprising a memory array comprising memory cells and a control logic component electrically connected to the memory array. At least one of the memory cells comprises a multilevel wiring structure comprising interconnect structures, where the interconnect structures comprise a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. Related apparatus, memory devices, and methods are also disclosed.
4
US2021013302A1
CAPACITOR AND MANUFACTURING METHOD THEREFOR
Publication/Patent Number: US2021013302A1 Publication Date: 2021-01-14 Application Number: 17/033,874 Filing Date: 2020-09-27 Inventor: Lu, Bin   Shen, Jian   Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.   IPC: H01L49/02 Abstract: A capacitor includes: at least one multi-wing structure including N axes and M wings, where the N axes extend along a first direction, and the M wings are a convex structure formed by extending from side walls of the N axes toward a direction perpendicular to the first direction, a first wing of the M wings and the N axes are formed of a first conductive material, and other wings are formed of a second conductive material; a conductive structure cladding the multi-wing structure; a dielectric layer disposed between the multi-wing structure and the conductive structure to isolate the multi-wing structure from the conductive structure; a first external electrode electrically connected to some or all multi-wing structures; and a second external electrode electrically connected to the conductive structure.
5
US10950494B2
Semiconductor device including first and second contact layers and manufacturing method
Publication/Patent Number: US10950494B2 Publication Date: 2021-03-16 Application Number: 16/251,729 Filing Date: 2019-01-18 Inventor: Huesken, Holger   Pfirsch, Frank Dieter   Assignee: Infineon Technologies AG   IPC: H01L21/768 Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.
6
CN109256358B
一种导电栓塞的制备方法及具有导电栓塞的半导体器件
Grant
Publication/Patent Number: CN109256358B Publication Date: 2021-03-30 Application Number: 201710574932.0 Filing Date: 2017-07-14 Inventor: 不公告发明人   Assignee: 长鑫存储技术有限公司   IPC: H01L21/768 Abstract: 本发明公开了一种导电栓塞的制备方法,包括:提供一开设有孔洞的衬底,孔洞的第一开口端暴露于衬底表面;形成第一导电沉积膜在衬底表面上,第一导电沉积膜包括具有空隙的第一栓塞部,局部填充在孔洞中,空隙为细长状以使空隙的端部超出孔洞的第一开口端;扩大空隙的端部,以使空隙的端部扩大形成为暴露于第一导电沉积膜的第二开口端,第二开口端的孔径为第一开口端的孔径30%~70%,包括端点值;形成第二导电沉积膜在第一导电沉积膜上,第二导电沉积膜包括第二栓塞部,填充在具有第二开口端的空隙中;及去除在衬底表面上的第一导电沉积膜与第二导电沉积膜,以形成电性隔离的导电栓塞。此方法缩小空隙体积,或消除空隙,得到电阻低、可靠性高的导电栓塞。
7
US2021020503A1
MICROELECTRONIC DEVICES COMPRISING MANGANESE-CONTAINING CONDUCTIVE STRUCTURES, AND RELATED ELECTRONIC SYSTEMS
Publication/Patent Number: US2021020503A1 Publication Date: 2021-01-21 Application Number: 16/856,824 Filing Date: 2020-04-23 Inventor: Ishii, Kentaro   Assignee: Micron Technology, Inc.   IPC: H01L21/768 Abstract: A microelectronic device comprises a first conductive material comprising copper, a conductive plug comprising tungsten in electrical communication with the first conductive material, and manganese particles dispersed along an interface between the first conductive material and the conductive plug. Related electronic systems and related methods are also disclosed.
8
US2021020502A1
INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES
Publication/Patent Number: US2021020502A1 Publication Date: 2021-01-21 Application Number: 17/061,062 Filing Date: 2020-10-01 Inventor: Yoo, Hui Jae   Indukuri, Tejaswi K.   Chebiam, Ramanan V.   Clarke, James S.   Assignee: Intel Corporation   IPC: H01L21/768 Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.
9
CN106601664B
形成有选择性沉积蚀刻停止层的自对准通孔的方法和装置
Grant
Publication/Patent Number: CN106601664B Publication Date: 2021-02-19 Application Number: 201610651829.7 Filing Date: 2016-08-10 Inventor: 吴永旭   陈海清   蔡荣训   眭晓林   包天一   Assignee: 台湾积体电路制造股份有限公司   IPC: H01L21/768 Abstract: 在衬底上方形成互连结构的层。该层含有层间介电(ILD)材料和在ILD中设置的金属线。在ILD上但是不在金属线上形成第一蚀刻停止层。通过选择性原子层沉积(SALD)工艺形成第一蚀刻停止层。在第一蚀刻停止层上方形成第二蚀刻停止层。在第一和第二蚀刻停止层之间存在较高的蚀刻选择性。形成的通孔至少部分地与金属线对准,并且电连接至金属线。在通孔的形成期间,第一蚀刻停止层防止ILD被蚀刻穿过。本发明的实施例还涉及形成有选择性沉积蚀刻停止层的自对准通孔的方法和装置。
10
CN112510014A
内连线结构
Public
Publication/Patent Number: CN112510014A Publication Date: 2021-03-16 Application Number: 202010959996.4 Filing Date: 2020-09-14 Inventor: 杨士亿   李明翰   眭晓林   Assignee: 台湾积体电路制造股份有限公司   IPC: H01L23/532 Abstract: 本发明实施例公开了一种内连线结构。一种例示性的内连线结构,包括:第一接触部件,于第一介电层中;第二介电层,于第一介电层上方;第三介电层,于第二介电层上方;第二接触部件,延伸穿过第二介电层及第三介电层;及石墨烯层,于第二接触部件及第三介电层之间。
11
CN112563242A
半导体装置
Public
Publication/Patent Number: CN112563242A Publication Date: 2021-03-26 Application Number: 202010776850.6 Filing Date: 2020-08-05 Inventor: 刘承勇   李钟振   金洛焕   郑恩志   洪元赫   Assignee: 三星电子株式会社   IPC: H01L23/528 Abstract: 提供了半导体装置。所述半导体装置包括设置在基底上并具有第一沟槽的第一层间绝缘膜。第一下导电图案填充第一沟槽并且包括在与基底的上表面平行的第一方向上彼此间隔开的第一谷区域和第二谷区域。第一谷区域和第二谷区域朝向基底凹陷。第二层间绝缘膜设置在第一层间绝缘膜上并且包括暴露第一下导电图案的至少一部分的第二沟槽。上导电图案填充第二沟槽并且包括上阻挡膜和设置在上阻挡膜上的上填充膜。上导电图案至少部分地填充第一谷区域。
12
US10950496B2
Microelectronic devices comprising manganese-containing conductive structures, and related electronic systems
Publication/Patent Number: US10950496B2 Publication Date: 2021-03-16 Application Number: 16/856,824 Filing Date: 2020-04-23 Inventor: Ishii, Kentaro   Assignee: Micron Technology, Inc.   IPC: H01L23/532 Abstract: A microelectronic device comprises a first conductive material comprising copper, a conductive plug comprising tungsten in electrical communication with the first conductive material, and manganese particles dispersed along an interface between the first conductive material and the conductive plug. Related electronic systems and related methods are also disclosed.
13
US10950548B2
Semiconductor device
Publication/Patent Number: US10950548B2 Publication Date: 2021-03-16 Application Number: 15/903,908 Filing Date: 2018-02-23 Inventor: Sano, Yuichi   Kurokawa, Atsushi   Kobayashi, Kazuya   Assignee: MURATA MANUFACTURING CO., LTD.   IPC: H01L23/532 Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.
14
CN112530862A
半导体装置的形成方法
Public
Publication/Patent Number: CN112530862A Publication Date: 2021-03-19 Application Number: 202010980084.5 Filing Date: 2020-09-17 Inventor: 谌俊元   邱士权   游家权   张家豪   林天禄   林佑明   Assignee: 台湾积体电路制造股份有限公司   IPC: H01L21/768 Abstract: 一种半导体装置的形成方法,该方法包含形成第一导电部件于基板上。形成接触第一导电部件的导孔。导孔包含导电材料。对导孔的顶表面执行化学机械研磨(CMP)工艺。沉积层间介电(ILD)层于导孔上。形成沟槽于层间介电层中,以暴露导孔。以接触导孔的第二导电部件填充沟槽。第二导电部件包含与导电材料相同的材料。
15
US2021098285A1
FIELD EFFECT TRANSISTOR HAVING IMPROVED GATE STRUCTURES
Publication/Patent Number: US2021098285A1 Publication Date: 2021-04-01 Application Number: 16/583,984 Filing Date: 2019-09-26 Inventor: Laroche, Jeffrey R.   Bettencourt, John P.   Duval, Paul J.   Ip, Kelly P.   Assignee: Raytheon Company   IPC: H01L21/768 Abstract: A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.
16
CN112435958A
集成电路结构及其形成方法
Substantial Examination
Publication/Patent Number: CN112435958A Publication Date: 2021-03-02 Application Number: 202010873119.5 Filing Date: 2020-08-26 Inventor: 林志男   吴家宇   许凯翔   刘定一   Assignee: 台湾积体电路制造股份有限公司   IPC: H01L21/768 Abstract: 形成集成电路结构的方法包括在第一导电部件上方沉积蚀刻停止层,实施第一处理以使蚀刻停止层非晶化,在蚀刻停止层上方沉积介电层,蚀刻介电层以形成开口,蚀刻穿过蚀刻停止层以将开口延伸至蚀刻停止层中,以及用导电材料填充开口以形成第二导电部件。本发明的实施例还提供了一种集成电路结构。
17
US2021082831A1
ELECTRO-MIGRATION BARRIER FOR INTERCONNECT
Publication/Patent Number: US2021082831A1 Publication Date: 2021-03-18 Application Number: 17/104,534 Filing Date: 2020-11-25 Inventor: Sung, Su-jen   Chang, Chih-chiang   Chen, Chia-ho   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/532 Abstract: The present disclosure relates to an integrated circuit having a conductive interconnect disposed on a dielectric over a substrate. A first liner is arranged along an upper surface of the conductive interconnect. A barrier layer is arranged along a lower surface of the conductive interconnect and contacts an upper surface of the dielectric. The barrier layer and the first liner surround the conductive interconnect. A second liner is located over the first liner and has a lower surface contacting the upper surface of the dielectric.
18
CN110137153B
半导体装置及其形成方法
Grant
Publication/Patent Number: CN110137153B Publication Date: 2021-03-30 Application Number: 201810133700.6 Filing Date: 2018-02-09 Inventor: 刘志建   陈品宏   郑存闵   陈意维   Assignee: 联华电子股份有限公司   福建省晋华集成电路有限公司   IPC: H01L23/532 Abstract: 本发明公开一种半导体装置及其形成方法,该半导体装置包含一基底、一介电层、一第一钨层以及一第二钨层。介电层是设置在该基底上,且包含一第一开口以及一第二开口,该第二开口具有大于该第一开口的孔径。第一钨层设置于该第一开口与该第二开口内,并填满该第一开口。第二钨层,设置在该第一钨层上,该第二钨层的管芯尺寸自该第二钨层的底面朝向顶面而逐渐增加。
19
CN108573913B
半导体结构及其形成方法
Grant
Publication/Patent Number: CN108573913B Publication Date: 2021-04-02 Application Number: 201710141361.1 Filing Date: 2017-03-10 Inventor: 邓浩   周鸣   Assignee: 中芯国际集成电路制造(上海)有限公司   中芯国际集成电路制造(北京)有限公司   IPC: H01L21/768 Abstract: 一种半导体结构及其形成方法,其中方法包括:提供基底,所述基底上具有第一介质层,所述第一介质层内具有第一互连结构,所述第一介质层暴露出所述第一互连结构的顶部表面;采用原子层沉积工艺在所述第一介质层和第一互连结构的顶部表面形成第一停止层;采用物理气相沉积工艺在所述第一停止层的顶部表面形成第二停止层。所述方法提高了半导体结构的性能。
20
CN112490180A
半导体结构及其形成方法
Substantial Examination
Publication/Patent Number: CN112490180A Publication Date: 2021-03-12 Application Number: 201910866417.9 Filing Date: 2019-09-12 Inventor: 张田田   张浩   肖张茹   荆学珍   Assignee: 中芯国际集成电路制造(上海)有限公司   中芯国际集成电路制造(北京)有限公司   IPC: H01L21/768 Abstract: 一种半导体结构及其形成方法,包括:提供衬底,所述衬底内具有半导体材料结构;在衬底表面形成介质层,所述介质层内具有暴露出半导体材料结构顶部表面的第一开口;在第一开口侧壁表面形成绝缘层,绝缘层内掺杂有改性离子;在半导体材料结构表面、以及介质层顶部表面形成初始接触层;在初始接触层表面形成保护层;在保护层顶部表面以及绝缘层的侧壁表面形成填充第一开口的导电插塞;进行退火处理,使绝缘层、改性离子以及导电插塞反应,在导电插塞的侧壁表面形成阻挡层。在本发明的技术方案中,形成阻挡层的厚度降低,减小了占据导电插塞与保护层形成的空间,有效增大了导电插塞、保护层与接触层之间的接触面积,进而减小了接触电阻。
Total 500 pages