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1
CN108140639B
包括集成电路(IC)封装之间的间隙控制器的层叠封装(PoP)器件
Grant
Publication/Patent Number: CN108140639B Publication Date: 2021-02-26 Application Number: 201680057329.9 Filing Date: 2016-09-29 Inventor: R·库马   C-k·金   B·罗杰曼   Assignee: 高通股份有限公司   IPC: H01L25/065 Abstract: 一种层叠封装(PoP)器件包括第一封装、耦合至第一封装的第二封装、以及位于第一封装与第二封装之间的至少一个间隙控制器,其中该至少一个间隙控制器被配置成提供第一封装与第二封装之间的最小间隙。第一封装包括第一电子封装组件(例如,第一管芯)。在一些实现中,该至少一个间隙控制器耦合至第一封装、但是不与第二封装耦合。该至少一个间隙控制器位于第一封装的中心之上或周围。该至少一个间隙控制器可以位于第一电子封装组件(例如,第一管芯)与第二封装之间。层叠封装(PoP)器件可以包括第一封装与第二封装之间的包封层。
2
CN212848394U
一种多层芯片的封装结构
Grant
Publication/Patent Number: CN212848394U Publication Date: 2021-03-30 Application Number: 202021820381.5 Filing Date: 2020-08-26 Inventor: 胡慧雄   李龙   解维虎   Assignee: 深圳市金誉半导体股份有限公司   IPC: H01L25/065 Abstract: 本实用新型提供了一种多层芯片的封装结构,包括:从上至下依次层叠设置的两个以上芯片组件,每个所述芯片组件包括基板、连接在所述基板上的芯片单体和设置在所述基板上的若干通孔,其中,所述通孔的大小取决于所述基板所处的位置;金属架,所述金属架表面固定若干圆台状连接体;所述芯片组件均位于金属架上方,且所述通孔套在所述连接体上。通过形位配合实现连接体和基板之间的固定和连通的功能,从而可以对多层芯片进行初步封装,若检测到封装后的芯片连接不良时,可以直接拆卸返工校正,在校正好后将连接体和基板进行焊接。该封装方式的改变使得制备过程中出现连接不良的情况时,能够有效实现芯片组件之间的重新互连,降低制备成本。
3
US2021111159A1
SEMICONDUCTOR PACKAGE INCLUDING A FILLET LAYER
Publication/Patent Number: US2021111159A1 Publication Date: 2021-04-15 Application Number: 16/877,211 Filing Date: 2020-05-18 Inventor: Park, Sang-sick   Kim, Min Soo   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L25/065 Abstract: A semiconductor package includes a base substrate having a first semiconductor substrate, and a first protective layer covering a top side thereof. A first semiconductor chip is on the first protective layer. A first fillet layer fills a space between the first protective layer and the first semiconductor chip. A first side surface of the base substrate extends in a first direction, and second and third side surfaces extend in a second direction. The base substrate includes two corner regions and a side region between the corner regions. A first protective layer in the side region includes a first side trench which overlaps the first semiconductor chip. A part of the first fillet layer fills the first side trench.
4
CN112310052A
多芯片封装
Substantial Examination
Publication/Patent Number: CN112310052A Publication Date: 2021-02-02 Application Number: 202010742835.X Filing Date: 2020-07-29 Inventor: 陈永   D·加尼   Assignee: 意法半导体有限公司   IPC: H01L25/065 Abstract: 本公开涉及一种多芯片封装,包括第一集成电路和第二集成电路。第一集成电路包括具有第一导电层的第一侧、具有第二导电层的第二侧、以及边缘,第一导电层在与边缘相邻的位置处耦合到第二导电层。第二集成电路耦合到第一集成电路的第二导电层。
5
US2021111152A1
SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS
Publication/Patent Number: US2021111152A1 Publication Date: 2021-04-15 Application Number: 16/867,328 Filing Date: 2020-05-05 Inventor: Park, Hong-bum   Park, Jeong-hyun   Lee, Suk-won   Assignee: SK hynix Inc.   IPC: H01L25/065 Abstract: A semiconductor package includes a base substrate; a printed circuit board disposed on the base substrate; a first chip stack disposed on the base substrate on one side of the printed circuit board, and including first semiconductor chips offset-stacked in a first offset direction facing the printed circuit board; a second chip stack disposed on the first chip stack, and including second semiconductor chips offset-stacked in a second offset direction facing away from the printed circuit board; a third chip stack disposed on the base substrate on the other side of the printed circuit board, and including third semiconductor chips offset-stacked in the second offset direction; and a fourth chip stack disposed on the third chip stack, and including fourth semiconductor chips offset-stacked in the first offset direction, wherein the second and fourth chip stacks are electrically connected with the base substrate through the printed circuit board.
6
US2021104497A1
SEMICONDUCTOR APPARATUS
Publication/Patent Number: US2021104497A1 Publication Date: 2021-04-08 Application Number: 17/024,828 Filing Date: 2020-09-18 Inventor: Sakui, Koji   Ohba, Takayuki   Assignee: HONDA MOTOR CO., LTD.   TOKYO INSTITUTE OF TECHNOLOGY   IPC: H01L25/065 Abstract: A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; and a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips, wherein a semiconductor chip has at least one sub-memory array, and a penetration electrode penetrates through an outer circumferential part of the sub-memory array.
7
CN112447683A
堆叠管芯结构
Public
Publication/Patent Number: CN112447683A Publication Date: 2021-03-05 Application Number: 202010862945.X Filing Date: 2020-08-25 Inventor: 陈洁   陈宪伟   陈明发   Assignee: 台湾积体电路制造股份有限公司   IPC: H01L25/065 Abstract: 一种堆叠管芯结构包含基础管芯、顶部管芯和电连接到顶部管芯的导电端子。基础管芯包含基础半导体衬底、安置在基础半导体衬底上的基础内连线层和安置在基础内连线层上的基础接合层。顶部管芯堆叠在基础管芯上且电连接到基础管芯,其中顶部管芯包含顶部接合层、顶部半导体衬底、顶部内连线层、顶部导电衬垫和顶部接地通孔。顶部接合层混合接合到基础接合层。顶部内连线层安置在顶部半导体衬底上,且包含介电层、嵌入介电层中的导电层和连接导电层的导电通孔。导电衬垫和顶部接地通孔嵌入介电层中且安置在导电层上。
8
CN105633063B
半导体封装件
Grant
Publication/Patent Number: CN105633063B Publication Date: 2021-02-05 Application Number: 201510813432.9 Filing Date: 2015-11-23 Inventor: 李仁   Assignee: 三星电子株式会社   IPC: H01L25/065 Abstract: 提供了半导体封装件及其制造方法。半导体封装件包括:第一半导体芯片,具有第一电路图案;第二半导体芯片,设置在第一半导体芯片上且设置有第二电路图案;以及第一连接结构和第二连接结构,贯穿第一半导体芯片和第二半导体芯片。第一连接结构电连接到第一电路图案,并且可以与第二电路图案电分离。第二连接结构与第一电路图案电分离,并且可以电连接到第二电路图案。
9
US2021098425A1
SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS
Publication/Patent Number: US2021098425A1 Publication Date: 2021-04-01 Application Number: 16/899,359 Filing Date: 2020-06-11 Inventor: Lee, Chaesung   Kim, Jonghoon   Choi, Bokkyu   Sung, Kijun   Assignee: SK hynix Inc.   IPC: H01L25/065 Abstract: A semiconductor package may include: a chip stack including a plurality of semiconductor chips stacked in a vertical direction; vertical interconnectors, each having first ends that are connected to the plurality of semiconductor chips, respectively, and extending in the vertical direction; a molding layer covering the chip stack and the vertical interconnectors while exposing second ends of the vertical interconnectors; landing pads formed over one surface of the molding layer to be in contact with the second ends of the vertical interconnectors, respectively, wherein the landing pads are conductive and overlap the first ends of the vertical interconnectors, respectively; and a package redistribution layer electrically connected to the vertical interconnectors through the landing pads.
10
CN212659539U
用于多芯片封装的设备
Grant
Publication/Patent Number: CN212659539U Publication Date: 2021-03-05 Application Number: 202021529417.4 Filing Date: 2020-07-29 Inventor: 陈永   D·加尼   Assignee: 意法半导体有限公司   IPC: H01L25/065 Abstract: 本公开涉及一种用于多芯片封装的设备,包括第一集成电路和第二集成电路。第一集成电路包括具有第一导电层的第一侧、具有第二导电层的第二侧、以及边缘,第一导电层在与边缘相邻的位置处耦合到第二导电层。第二集成电路耦合到第一集成电路的第二导电层。根据本公开的用于多芯片封装的设备,在主IC的总体裸片面积最小增加的情况下,将一个或多个次集成电路或裸片耦合到较大的主IC或裸片上,同时维持与当前前端半导体过程的兼容性。
11
US2021020616A1
THREE-LAYER COLOR DISPLAY USING ACTIVE LED DIES
Publication/Patent Number: US2021020616A1 Publication Date: 2021-01-21 Application Number: 16/843,590 Filing Date: 2020-04-08 Inventor: Ray, William Johnstone   Lefebvre, Michael   Wagner, Darin   Blanchard, Richard A.   Assignee: Nthdegree Technologies Worldwide Inc.   IPC: H01L25/075 Abstract: Over a flexible substrate are deposited stacked pixel layers including a bottom layer of LEDs forming blue pixels, a middle layer of LEDs forming green pixels, and a top layer of LEDs forming red pixels. Each LED die comprises an LED portion and an integrated transistor portion. Applying a voltage to a control terminal of the transistor portion energizes the LED portion. The pixels are substantially transparent, due to the LEDs being microscopic and the pixel areas being much larger, to allow light from the underlying layers to pass through. The three layers of pixels are aligned so that a combination of a single top red pixel, a single underlying green pixel, and a single underlying blue pixel form a single multi-color pixel. The different layers have transparent column and row lines.
12
US10886194B2
Radiator component and heat dissipation system for power semiconductor device
Publication/Patent Number: US10886194B2 Publication Date: 2021-01-05 Application Number: 16/647,923 Filing Date: 2018-07-06 Inventor: Zhang, Sheng   Yao, Ji Long   Zhao, Yan Feng   Shi, Lei   Liu, Ze Wei   Assignee: SIEMENS AKTIENGESELSCHAFT   IPC: H01L23/467 Abstract: Embodiments disclose a radiator component and a heat dissipation system for a power semiconductor device. The radiator component for a power semiconductor device includes a heat dissipation body including an inner-ring substrate, an outer-ring substrate, and a plurality of heat sinks. In an embodiment, the outer-ring substrate surrounds the inner-ring substrate and the plurality of heat sinks are arranged between the inner-ring substrate and the outer-ring substrate. One or more first power semiconductor device arrangement positions are provided on an inner circumferential surface of the inner-ring substrate and one or more second power semiconductor device arrangement positions are arranged on an outer circumferential surface of the outer-ring substrate. The radiator component further includes a fan component. The embodiments can save on space, reduce costs, improve the heat dissipation efficiency, and avoid the problem of disturbances between a plurality of fans.
13
CN112514062A
具有在芯片与封装衬底之间提供电源连接的芯片互连桥的多芯片封装结构
Substantial Examination
Publication/Patent Number: CN112514062A Publication Date: 2021-03-16 Application Number: 201980048351.0 Filing Date: 2019-07-18 Inventor: J.鲁宾   L.克莱文格   C.l.阿尔文   Assignee: 国际商业机器公司   IPC: H01L23/538 Abstract: 提供了多芯片封装结构和用于构造多芯片封装结构的方法,其利用芯片互连桥器件,该芯片互连桥器件被设计为在封装结构中的相邻芯片(或裸片)之间提供高互连密度,以及通过所述芯片互连桥器件提供垂直电源分布迹线,以从封装衬底向连接到所述芯片互连桥器件的所述芯片供应电源(和接地)连接。
14
US2021098426A1
PACKAGING STRUCTURE, AND FORMING METHOD AND PACKAGING METHOD THEREOF
Publication/Patent Number: US2021098426A1 Publication Date: 2021-04-01 Application Number: 17/107,799 Filing Date: 2020-11-30 Inventor: Wang, Chaohong   Yang, Ke   Leng, Hanjian   Assignee: Shenzhen Goodix Technology Co., Ltd.   IPC: H01L25/065 Abstract: Some embodiments of the present disclosure provide a packaging structure, a forming method for a packaging structure and a packaging method for a packaging structure. The packaging structure includes a first semiconductor unit and a second semiconductor unit. The first semiconductor unit includes a wafer or a chip, the first semiconductor unit has a first surface on which at least one first conductive bump is provided. The second semiconductor unit is fixed on the first surface and includes a wafer or a chip. The second semiconductor unit has a second surface on which at least one second conductive bump is provided. The second surface and the first surface face to each other. The second conductive bump and the first conductive bump are oppositely arranged and fixed to each other.
15
CN109872737B
存储器装置
Grant
Publication/Patent Number: CN109872737B Publication Date: 2021-01-26 Application Number: 201810213700.7 Filing Date: 2018-03-15 Inventor: 中冈裕司   Assignee: 华邦电子股份有限公司   IPC: G11C7/10 Abstract: 本发明提供一种存储器装置。存储器装置包括第一芯片及第二芯片。第一芯片包括第一存储器阵列、第一信号缓冲器以及多个第一衬垫。第二芯片包括第二存储器阵列、第二信号缓冲器以及多个第二衬垫。第二信号缓冲器通过至少一导线耦接至第一信号缓冲器,且所述至少一导线穿越所述第一芯片与第二芯片之间的切割道。在所述第一芯片与所述第二芯片之间的所述切割道并未被切割的情况下,所述第一信号缓冲器及所述第二信号缓冲器通过所述至少一导线来传递信号,且所述第一存储器阵列及所述第二存储器阵列共同被连接至所述第一衬垫且不被连接至所述第二衬垫。
16
CN112242344A
三维集成电路结构及其制造方法
Substantial Examination
Publication/Patent Number: CN112242344A Publication Date: 2021-01-19 Application Number: 201910932389.6 Filing Date: 2019-09-29 Inventor: 陈宪伟   陈明发   叶松峯   Assignee: 台湾积体电路制造股份有限公司   IPC: H01L21/762 Abstract: 本发明实施例公开三维集成电路结构及形成所述三维集成电路结构的方法。所述三维集成电路结构中的一者包括第一管芯、多个第二管芯以及介电结构。所述第二管芯结合到所述第一管芯。所述介电结构设置在所述第二管芯之间。所述介电结构包括第一介电层及第二介电层。所述第一介电层具有侧壁及底部,所述侧壁的第一表面与所述底部的第一表面接触所述第二介电层且形成第一角度。所述侧壁的第二表面与所述底部的第二表面形成比所述第一角度小的第二角度。
17
CN107251216B
用于微电子结构中的互连垫的表面末道层
Grant
Publication/Patent Number: CN107251216B Publication Date: 2021-03-23 Application Number: 201580077003.8 Filing Date: 2015-02-25 Inventor: S.v.皮坦巴拉姆   K.o.李   Assignee: 英特尔公司   IPC: H01L23/48 Abstract: 可以在微电子结构中形成表面末道层,其中表面末道层可以包括多层夹层结构。因此,可以通过不同的材料层来满足夹层结构的所需要的特性,诸如顺从和抗电迁移,而不是尝试利用单个层来实现这些特性。在一个实施例中,多层夹层结构可以包括两层结构,其中接近焊料互连来形成第一层并且第一层包括形成与焊料互连的易延展接头的材料,以及第二层包括具有在第一层和互连垫之间形成的强抗电迁移的材料。在另外的实施例中,第三层可以邻近互连垫来形成,包括形成与互连垫的易延展接头的材料。
18
US2021066275A1
SEMICONDUCTOR MEMORY DEVICE
Publication/Patent Number: US2021066275A1 Publication Date: 2021-03-04 Application Number: 16/804,517 Filing Date: 2020-02-28 Inventor: Noro, Hiromi   Assignee: Kioxia Corporation   IPC: H01L25/18 Abstract: According to one embodiment, a semiconductor memory device includes a mounting board and memory dies. The memory dies include first pad electrodes, first pull-up circuits connected to the first pad electrodes, a first output circuit that outputs a first parameter to the first pull-up circuits, first pull-down circuits connected to the first pad electrodes, a second output circuit that outputs a second parameter to the first pull-down circuits, a second pad electrode, a second pull-up circuit connected to the second pad electrode, a third output circuit that is connected to the second pad electrode, a third pad electrode, a second pull-down circuit connected to the third pad electrode, and a fourth output circuit that is connected to the third pad electrode. The second pad electrode of the second memory die is connected to the third pad electrode of the first memory die.
19
CN212322986U
一种立体封装EEPROM存储器
Grant
Publication/Patent Number: CN212322986U Publication Date: 2021-01-08 Application Number: 202021023591.1 Filing Date: 2020-06-08 Inventor: 马玉华   孟庆福   王伟   汤凡   Assignee: 青岛欧比特宇航科技有限公司   IPC: H01L23/48 Abstract: 本实用新型公开了一种立体封装EEPROM存储器,包括基片单体和单体引脚,基片单体上设有单体引脚,多个基片单体垂直堆叠且对应的单体引脚依次上下对应成列,多个堆叠在一起的基片单体的左右两侧设有侧辅助板,两个侧辅助板的上端之间通过嵌合的方式设有封装辅助板,单体引脚依次贯穿侧辅助板,侧辅助板远离基片单体的一侧设有将多个竖直成列的单体引脚连通的金属连片,金属连片的下端向下穿出侧辅助板并弯曲形成接合引脚,使得多个基片单体能够立体封装在一起。本实用新型采用多个存储器基片单体堆叠且两侧设有侧辅助板夹住,形成一个立体封装结构,方便灌胶,且通过侧辅助板上的通孔增强固化胶与侧辅助板的附着力。
20
US2021043606A1
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
Publication/Patent Number: US2021043606A1 Publication Date: 2021-02-11 Application Number: 16/537,554 Filing Date: 2019-08-10 Inventor: Bowers, Shaun   Alapati, Ramakanth   Assignee: Amkor Technology Inc.   IPC: H01L25/065 Abstract: A packaged semiconductor device includes a substrate with first and second opposing major surfaces. A stacked semiconductor device structure is connected to the first major surface and includes a plurality of semiconductor die having terminals. Conductive interconnect structures electrically connect the terminals of the semiconductor dies together. The semiconductor dies are stacked together so that the terminals are exposed, and the stacked semiconductor device structure comprises a stepped profile. The conductive interconnect structures comprise a conformal layer that substantially follows the stepped profile.
Total 500 pages