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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
EP3772101A1
DISPLAY DEVICE
Publication/Patent Number: EP3772101A1 Publication Date: 2021-02-03 Application Number: 20172160.2 Filing Date: 2020-04-29 Inventor: Cho, Hyeon Gu   Choi, Min Soo   Yoon, Seok Gyu   Lyu, Jae Jin   Assignee: Samsung Display Co., Ltd.   IPC: H01L27/00 Abstract: A display device includes a display substrate, a light emitting element layer disposed on a surface of the display substrate and including display pixels, a sensing substrate having a surface attached to another surface of the display substrate, a sensing element layer disposed on another surface of the sensing substrate and including sending pixels that each sense light of a color, and a photorefractive layer disposed on the sensing element layer and including micro lenses.
2
CN112262471A
具有三维外观的车灯
Substantial Examination
Publication/Patent Number: CN112262471A Publication Date: 2021-01-22 Application Number: 201980039290.1 Filing Date: 2019-06-10 Inventor: 本杰明·萨尔茨曼   Assignee: 麦格纳国际公司   IPC: H01L27/00 Abstract: 一种照明装置、例如呈现三维对象的刹车灯组件包括多个微型发光二极管管芯,每个微型发光二极管管芯的尺寸约为0.2mm×0.2mm。微型发光二极管管芯被布置在印刷电路板或柔性电路的连续表面上。每个微型发光二极管管芯能够由控制器单独或成组寻址以用于调节亮度和/或颜色,并且控制器被配置成以一个或多个不同的图案点亮多个微型发光二极管管芯,以显现为三维对象。控制器被配置成以时变图案来使三维对象动画化,该时变图案例如可以使三维对象显现成移入电路上的平面或与电路平行的平面中或者从所述表面中移出。可以以跳动的图案使三维对象动画化,这可以使其更有趣或增强相关的信号发送状况的可见性。
3
US10886499B2
Light emitting display apparatus and method of manufacturing the same
Publication/Patent Number: US10886499B2 Publication Date: 2021-01-05 Application Number: 16/512,032 Filing Date: 2019-07-15 Inventor: Kim, Goeun   Shin, Younghoon   Assignee: LG DISPLAY CO., LTD.   IPC: H01L51/00 Abstract: A light emitting display apparatus includes a passivation layer on a thin film transistor, a light emitting diode on the passivation layer, the light emitting diode having an anode, a light emitting layer on the anode, and a cathode on the light emitting layer, and a hydrogen absorbing layer on the light emitting diode, the hydrogen absorbing layer including an inorganic material having a mass percentage of 0.08% to 50%.
4
US10908333B2
Optical film, polarization plate, and image display device
Publication/Patent Number: US10908333B2 Publication Date: 2021-02-02 Application Number: 16/482,116 Filing Date: 2018-01-30 Inventor: Nomura, Takahisa   Hamada, Takanori   Nakashima, Masataka   Hata, Kentaro   Nakamura, Hiroshi   Nakagawa, Hiroki   Assignee: Dai Nippon Printing Co., Ltd.   IPC: H01L27/00 Abstract: Provided is an optical film 10 including a light-transmitting base material 11 and a light-transmitting functional layer 12 provided on one surface of the light-transmitting base material 11, wherein the optical film 10 has a spectral transmittance of less than 1% at a wavelength of 380 nm, a spectral transmittance of 10% or more and less than 60% at a wavelength of 410 nm, and a spectral transmittance of 70% or more at a wavelength of 440 nm, and wherein the light-transmitting functional layer 12 has a film thickness of 9 μm or less.
5
CN107004639B
衬底制造方法
Grant
Publication/Patent Number: CN107004639B Publication Date: 2021-02-05 Application Number: 201580037075.X Filing Date: 2015-07-06 Inventor: 李光雄   陈全胜   尤金·a·菲茨杰拉德   K·李永坚   Assignee: 麻省理工学院   南洋理工大学   IPC: H01L21/8238 Abstract: 公开了一种衬底(270)制造方法(200)。该方法包括:提供(202)第一半导体衬底(250),该衬底包括已至少部分处理的CMOS器件层以及第一晶片材料层;将承载衬底键合(204)至所述已部分处理的CMOS器件层,并去除(206)所述第一晶片材料层;提供第二半导体衬底,该衬底具有不同于硅的第二晶片材料层;通过将所述第二晶片材料层键合至所述已部分处理的CMOS器件层而将所述第一和第二半导体衬底键合(208),以形成结合衬底(268);以及将所述承载衬底从所述结合衬底移除(210),以暴露所述已部分处理的CMOS器件层的至少一部分。
6
US10916732B2
Display panel
Publication/Patent Number: US10916732B2 Publication Date: 2021-02-09 Application Number: 16/466,305 Filing Date: 2019-01-04 Inventor: Tang, Yuejun   Li, Xueyun   Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.   IPC: H01L27/00 Abstract: A display panel is provided and includes a display region including a plurality of sub pixel regions arranged in an array, wherein each of the sub pixel regions comprises a light emitting region and a non-light emitting region; a black array layer formed in the non-light emitting regions, the black array is used to shield the metal layer to reflect and absorb the environment light, to improve a light output rate and to improve a contrast ratio of the display device.
7
US10901280B2
Array substrate and display panel
Publication/Patent Number: US10901280B2 Publication Date: 2021-01-26 Application Number: 16/252,731 Filing Date: 2019-01-21 Inventor: Yu, Pengfei   Zhang, Jiawei   Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.   IPC: H01L27/00 Abstract: An array substrate may include a display area and a non-display area surrounding the display area. The display area may include at least one antistatic wiring; and a plurality of scan lines. The at least one antistatic wiring may be configured to conduct static electricity, and the at least one antistatic wiring and the plurality of scan lines may be interlaced and insulated. The at least one antistatic wiring may include a first wiring portion and a second wiring portion adjacent to each other. The first wiring portion and the second wiring portion may be located in different layers.
8
US10897590B2
Solid-state imaging apparatus and method of driving the same
Publication/Patent Number: US10897590B2 Publication Date: 2021-01-19 Application Number: 16/178,396 Filing Date: 2018-11-01 Inventor: Ishii, Motonori   Matsunaga, Yoshiyuki   Hirose, Yutaka   Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.   IPC: H01L27/00 Abstract: An imaging device includes a photoelectric converter generating signal charge; a charge storage region storing the signal charge; a first transistor having a gate coupled to the charge storage region; a second transistor having a source and a drain; and voltage supply circuitry supplying voltages varying with time. An output of the first transistor is fed back to the second transistor and is supplied to the charge storage region. A reset operation for discharging the signal charge in the charge storage region includes a first reset operation and a second reset operation. In the first reset operation, the second transistor changes from an OFF state to an ON state and then changes to an OFF state. In the second reset operation, the voltage supply circuitry supplies the voltages to a gate of the second transistor so that the second transistor gradually changes from an OFF state to an ON state.
9
CN105580136B
半导体装置和固体摄像器件
Grant
Publication/Patent Number: CN105580136B Publication Date: 2021-02-19 Application Number: 201480053552.7 Filing Date: 2014-09-19 Inventor: 香川恵永   藤井宣年   深沢正永   金口时久   萩本贤哉   青柳健一   三桥生枝   Assignee: 索尼公司   IPC: H01L27/00 Abstract: 本技术涉及能够以更简单的方式来提高抗裂性的半导体装置和固体摄像器件。所述半导体装置具有:上侧基板,其包括Si基板和层叠于该Si基板上的布线层;以及下侧基板,其包括Si基板和层叠于该Si基板上的布线层,所述下侧基板被接合至所述上侧基板。此外,在所述上侧基板中形成有引线接合用或探测用焊盘,而且,在位于所述引线接合用或探测用焊盘与所述下侧基板的所述Si基板之间的各个所述布线层中以呈放射状层叠的方式设置有用于保护所述引线接合用或探测用焊盘的拐角部分或侧边部分的焊盘。本技术能够被应用于固体摄像器件。
10
US10886351B2
Display device
Publication/Patent Number: US10886351B2 Publication Date: 2021-01-05 Application Number: 16/263,635 Filing Date: 2019-01-31 Inventor: Maruyama, Satoshi   Assignee: Japan Display Inc.   IPC: H01L27/00 Abstract: A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.
11
US10910410B2
Flexible array substrate, flexible display device and method of assembling the same
Publication/Patent Number: US10910410B2 Publication Date: 2021-02-02 Application Number: 16/262,240 Filing Date: 2019-01-30 Inventor: Zhu, Xiaolong   Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.   BOE TECHNOLOGY GROUP CO.. LTD   IPC: H01L27/00 Abstract: A flexible array substrate has a main display area, and includes a flexible substrate and a plurality of signal connecting portions. The flexible substrate includes at least one bent portion extending from at least one side of the main display area. The plurality of signal connecting portions are disposed at a side of the at least one bent portion away from the main display area. A plurality of signal lines are disposed on a first surface of the flexible substrate in the main display area. The plurality of signal connecting portions are configured to electrically connect the plurality of signal lines to at least one driving circuit. The at least one bent portion is configured to bend toward a second surface of the flexible substrate opposite to the first surface.
12
US10923453B2
Bonding apparatus and method for using the same
Publication/Patent Number: US10923453B2 Publication Date: 2021-02-16 Application Number: 16/127,376 Filing Date: 2018-09-11 Inventor: Kim, Byoung Yong   Hwang, Jeong Ho   Assignee: SAMSUNG DISPLAY CO., LTD.   IPC: H01L27/00 Abstract: A bonding apparatus for bonding a driving circuit to a display panel includes: a bonding stage unit on which the display panel is supported in bonding the driving circuit to the display panel; a head unit located above the bonding stage unit and with which ultrasonic waves are applied to the driving circuit to couple the driving circuit with a bonding area of the display panel supported on the bonding stage unit; and a protrusion disposed at an edge portion of the bonding stage unit, the edge portion corresponding to an end of the display panel at which the bonding area is disposed.
13
US10916738B2
Display panel and manufacturing method of the display panel, display device
Publication/Patent Number: US10916738B2 Publication Date: 2021-02-09 Application Number: 16/466,499 Filing Date: 2018-12-03 Inventor: Sun, Shi   Xie, Xuewu   Liu, Hao   Zhang, Ameng   Ai, Yu   Liu, Bowen   Kong, Yubao   Assignee: Hefei Xinsheng Optoelectronics Technology Co., Ltd.   BOE Technology Group Co., Ltd.   IPC: H01L27/00 Abstract: The present disclosure provides a display panel, a manufacturing method of the display panel, and a display device. The manufacturing method includes: forming an auxiliary cathode layer; forming at least one tip structure on the auxiliary cathode layer; forming a main cathode layer, wherein the at least one tip structure is between the auxiliary cathode layer and the main cathode layer; and forming at least one connection between the main cathode layer and the auxiliary cathode layer by discharging at the at least one tip structure, wherein the at least one connection is electrically connected to the main cathode layer and the auxiliary cathode layer respectively.
14
US10906305B2
Liquid ejection head
Publication/Patent Number: US10906305B2 Publication Date: 2021-02-02 Application Number: 16/543,317 Filing Date: 2019-08-16 Inventor: Teshima, Takayuki   Assignee: Canon Kabushiki Kaisha   IPC: B41J2/14 Abstract: A liquid ejection head includes, a multilayer wiring layer having a plurality of wiring layers laid one on the other and an insulating layer enveloping the plurality of wiring layers, an ejection orifice forming member arranged on one of the oppositely disposed surfaces of the multilayer wiring layer and having an ejection orifice formed therethrough to eject liquid and a through-hole electrode arranged in a through hole running through the multilayer wiring layer between the one and the other surfaces of the multilayer wiring layer. The plurality of wiring layers includes a first wiring layer having a surface located closest to the ejection orifice forming member and the through-hole electrode is held in contact with at least one surface of the plurality of wiring layers different from the surface of the first wiring layer and is electrically connected to the plurality of wiring layers.
15
US10910450B2
Chip on film package and display device
Publication/Patent Number: US10910450B2 Publication Date: 2021-02-02 Application Number: 16/431,714 Filing Date: 2019-06-04 Inventor: Huang, Ying-neng   Assignee: Novatek Microelectronics Corp.   IPC: H01L27/00 Abstract: A chip on film package structure including a flexible film and a chip is provided. The flexible film includes a main body and a first wing body. The main body includes a main bonding portion configured to be bonded to a first substrate. The first wing body includes a first extending part and a first bent part. The first extending part is extended from a side of the main body. The first bent part is configured to be bent to a second substrate and having a first wing bonding portion. The first wing bonding portion is configured to be bonded to the second substrate. The first substrate and the second substrate are stacked on top of each other. The chip mounted on and electrically connected to the main body. A display device is also provided.
16
US10916639B1
Semiconductor device structure and method for preparing the same
Publication/Patent Number: US10916639B1 Publication Date: 2021-02-09 Application Number: 16/511,602 Filing Date: 2019-07-15 Inventor: Lin, Yuan-yuan   Assignee: Nanya Technology Corporation   IPC: H01L27/00 Abstract: The present application discloses a semiconductor device structure and a method for preparing the same. The method includes forming a ring structure over a substrate; performing an etching process to form an annular semiconductor fin under the ring structure; forming a lower source/drain region on the surface of the substrate in contact with a bottom portion of the annular semiconductor fin; forming an inner gate structure in contact with an inner sidewall of the annular semiconductor fin and forming an outer gate structure in contact with an outer sidewall of the annular semiconductor fin; and forming an upper source/drain region on an upper portion of the annular semiconductor fin.
17
CN112219274A
半导体装置和半导体装置的制造方法
Public
Publication/Patent Number: CN112219274A Publication Date: 2021-01-12 Application Number: 201980037069.2 Filing Date: 2019-06-13 Inventor: 羽根田雅希   Assignee: 索尼半导体解决方案公司   IPC: H01L21/768 Abstract: 提供了一种进一步减小以任意布局配置的配线的配线间电容的半导体装置。半导体装置(1)设置有:第一配线间绝缘层(120),其设置在基板(100)上,并在与基板相反的一侧具有凹部;第一配线层(130),其设置在第一配线间绝缘层的凹部的内部;密封膜(140),其沿着第一配线层和第一配线间绝缘层的凹凸形状设置;第二配线间绝缘层(220),其以覆盖凹部的方式设置在第一配线间绝缘层上,并且具有与凹部相对的平坦表面;以及空隙(150),其设置在第二配线间绝缘层和第一配线层与第一配线间绝缘层之间。
18
US10923549B2
Display apparatus including a shielding conductive layer
Publication/Patent Number: US10923549B2 Publication Date: 2021-02-16 Application Number: 16/713,735 Filing Date: 2019-12-13 Inventor: Lee, Wonse   Kim, Kyunghoon   Assignee: SAMSUNG DISPLAY CO., LTD.   IPC: H01L27/00 Abstract: A display apparatus including a shielding conductive layer is disclosed. The display apparatus includes a substrate, a driving thin film transistor disposed on the substrate, wherein the driving thin film transistor includes a driving semiconductor layer and a driving gate electrode, a scan line overlapping the substrate and extending in a first direction, a data line extending in a second direction crossing the first direction, wherein the data line is insulated from the scan line by an insulating layer, a node connection line disposed on a same layer as the scan line, and a shielding conductive layer disposed between the data line and the node connection line, in which a first end of the node connection line is connected to the driving gate electrode via a first node contact hole.
19
US10916561B2
Method of fabricating semiconductor device
Publication/Patent Number: US10916561B2 Publication Date: 2021-02-09 Application Number: 16/374,450 Filing Date: 2019-04-03 Inventor: Pillai, Karthik   Chae, Soo Doo   Han, Sangcheol   Assignee: Tokyo Electron Limited   IPC: H01L21/00 Abstract: A method is provided for forming a semiconductor device. The method includes forming a vertical film stack containing a sacrificial layer on a substrate and dielectric layers alternatingly and repeatedly stacked on the sacrificial layer, removing the sacrificial layer to form a horizontal channel above the substrate, depositing a conformal dielectric layer in the horizontal channel, etching trenches in the vertical film stack that connect to the horizontal channel. The method further includes removing the conformal dielectric layer from the horizontal channel, filling the horizontal channel and the trenches with a first electrically conductive material, removing the first electrically conductive material from the trenches, and filling the trenches with a second electrically conductive material.
20
US10923491B2
Hybrid bonding contact structure of three-dimensional memory device
Publication/Patent Number: US10923491B2 Publication Date: 2021-02-16 Application Number: 16/821,757 Filing Date: 2020-03-17 Inventor: Lu, Zhenyu   Yang, Simon Shi-ning   Pan, Feng   Yang, Steve Weiyi   Chen, Jun   Wu, Guanping   Shi, Wenguang   Cheng, Weihua   Assignee: Yangtze Memory Technologies Co., Ltd.   IPC: H01L27/00 Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit. The array interconnection layer is bonded on the peripheral interconnection layer, such that the peripheral circuit is electrically connected with at least one through array contact.
Total 500 pages