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1
US2021043776A1
THIN FILM TRANSISTOR, PIXEL STRUCTURE, DISPLAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE
Publication/Patent Number: US2021043776A1 Publication Date: 2021-02-11 Application Number: 16/966,873 Filing Date: 2019-12-24 Inventor: Cheng, Hongfei   Assignee: Beijing BOE Technology Development Co., Ltd.   BOE TECHNOLOGY GROUP CO., LTD.   IPC: H01L29/786 Abstract: A thin film transistor is provided to include a gate, an active layer, a first electrode and a second electrode. The first electrode includes at least two first conductive parts extending in a first direction and a first connection part extending in a second direction intersecting the first direction. The at least two first conductive parts are arranged at intervals along the second direction and a first end of each of the at least first conductive parts is coupled to the first connection part, and two adjacent ones of the at least two first conductive parts form a first U-shaped opening with the first connection part. The second electrode includes at least one second conductive part extending in the first direction, a first end of the second conductive part proximal to the first connection part is in the first U-shaped opening.
2
US2021091226A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2021091226A1 Publication Date: 2021-03-25 Application Number: 17/111,810 Filing Date: 2020-12-04 Inventor: Tsubuku, Masashi   Sakamoto, Michiaki   Okada, Takashi   Kaneko, Toshiki   Toda, Tatsuya   Assignee: Japan Display Inc.   IPC: H01L29/786 Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.
3
CN112466932A
晶体管外延结构及其制备方法
Substantial Examination
Publication/Patent Number: CN112466932A Publication Date: 2021-03-09 Application Number: 202011375926.0 Filing Date: 2020-11-30 Inventor: 陈伟华   Assignee: 泉芯集成电路制造(济南)有限公司   IPC: H01L29/417 Abstract: 本发明的实施例提供了一种晶体管外延结构及其制备方法,涉及微电子技术领域,该晶体管外延结构包括:衬底基层;生长在所述衬底基层上的第一金属层和缓冲层,其中所述缓冲层间隔设置于所述第一金属层的相对两侧;以及生长在所述缓冲层上的第二金属层;其中,所述缓冲层用于阻碍所述第二金属层向所述衬底基层扩散。通过设置缓冲层,能够阻绝第二金属层和衬底基层,阻碍第二金属层中的正价元素向衬底基层扩散,从而防止第二金属层向衬底基层扩散。相较于现有技术,本发明提供的晶体管外延结构,能够减缓外延材料中的三价硼元素或者五价磷元素等正价元素会在后续制程时向硅基层扩散,有效减缓漏电现象,提升元件性能。
4
CN112382565A
氧化物层中深孔铝的填充方法
Substantial Examination
Publication/Patent Number: CN112382565A Publication Date: 2021-02-19 Application Number: 202011262136.1 Filing Date: 2020-11-12 Inventor: 韩为鹏   邓斌   Assignee: 北京北方华创微电子装备有限公司   IPC: H01L21/28 Abstract: 本发明公开了一种氧化物层中深孔铝的填充方法,包括:在氧化层的上表面、深孔的孔壁及深孔的底部沉积金属钛和氮化钛,形成粘附层;在粘附层上沉积金属钨,形成阻挡层;在阻挡层上沉积金属铝,形成铝薄膜;在铝薄膜上以预设温度沉积金属铝至完全填充深孔;在粘附层沉积金属钨作为阻挡层,可以在相对较薄的厚度下,提高对热铝扩散的阻碍作用,同时金属钨的电阻率较氮化钛低,对铝的电学性能影响较小。
5
US10950700B2
Semiconductor device and manufacturing method of semiconductor device
Publication/Patent Number: US10950700B2 Publication Date: 2021-03-16 Application Number: 16/189,563 Filing Date: 2018-11-13 Inventor: Choi, Kang Sik   Assignee: SK hynix Inc.   IPC: H01L29/417 Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
6
CN106024868B
半导体装置
Grant
Publication/Patent Number: CN106024868B Publication Date: 2021-04-13 Application Number: 201610126260.2 Filing Date: 2016-03-07 Inventor: 尹彰燮   具滋悦   金相吉   Assignee: 三星电子株式会社   IPC: H01L29/417 Abstract: 提供了一种半导体装置,所述半导体装置包括:多个有源图案,从基底突出;栅极结构,与多个有源图案交叉;多个源区/漏区,分别在栅极结构的相对的侧面处的多个有源图案上;源/漏接触件,与多个有源图案交叉,每个源/漏接触件共同连接到源/漏接触件下方的源区/漏区,多个源区/漏区中的每个包括第一部分和第二部分,第一部分与多个源区/漏区下方的有源图案的顶表面接触,第一部分的宽度随着距基底的距离增大而增大,第二部分从第一部分延伸,第二部分的宽度随着距基底的距离增大而减小,源/漏接触件的底表面比第一部分与第二部分之间的界面低。
7
US2021066296A1
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Publication/Patent Number: US2021066296A1 Publication Date: 2021-03-04 Application Number: 16/798,979 Filing Date: 2020-02-24 Inventor: Kutsukake, Hiroyuki   Akou, Masayuki   Assignee: KIOXIA CORPORATION   IPC: H01L27/092 Abstract: A semiconductor device includes: two first semiconductor regions of a first conductivity type spaced apart from each other; a second semiconductor region of a second conductivity type provided between the two first semiconductor regions; a first insulator region surrounding the two first semiconductor regions and the second semiconductor region; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the second conductivity type, the fourth semiconductor region surrounding the third semiconductor region and the first insulator region and having an impurity concentration of the second conductivity type lower than an impurity concentration of the third semiconductor region; a second insulator region that surrounds the fourth semiconductor region; a conductor layer provided over the second semiconductor region; two first contact plugs; a second contact plug provided on the conductor layer; and a third contact plug provided on the third semiconductor region.
8
US2021091123A1
THIN FILM TRANSISTOR ASSEMBLY, ARRAY SUBSTRATE AND DISPLAY PANEL
Publication/Patent Number: US2021091123A1 Publication Date: 2021-03-25 Application Number: 16/825,006 Filing Date: 2020-03-20 Inventor: Ren, Yanwei   Tang, Wulijibaier   Li, Xiaoguang   Xu, Jingyi   Wang, Yuelin   Jia, Lei   Yu, Yanan   Zhi, Guolei   Assignee: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.   BOE TECHNOLOGY GROUP CO., LTD.   IPC: H01L27/12 Abstract: Embodiments of the present disclosure provide a thin film transistor assembly, an array substrate and a display panel. The thin film transistor assembly includes a first thin film transistor and a second thin film transistor disposed on a substrate. The first thin film transistor includes a first source electrode, a first drain electrode, and a first active layer. The second thin film transistor includes a second source electrode. The first source electrode is disposed on a side of the first active layer facing towards the substrate. The first drain electrode is disposed on a side of the first active layer facing away from the substrate. An orthogonal projection of the first source electrode on the substrate overlaps an orthogonal projection of the second source electrode on the substrate.
9
US10944014B2
Semiconductor device
Publication/Patent Number: US10944014B2 Publication Date: 2021-03-09 Application Number: 16/513,826 Filing Date: 2019-07-17 Inventor: Yamazaki, Shunpei   Shimomura, Akihisa   Sato, Yuhei   Yamane, Yasumasa   Yamamoto, Yoshitaka   Suzawa, Hideomi   Tanaka, Tetsuhiro   Okazaki, Yutaka   Okuno, Naoki   Ishiyama, Takahisa   Assignee: Semiconductor Energy Laboratory Co., Ltd.   IPC: H01L29/786 Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.
10
US2021043742A1
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Publication/Patent Number: US2021043742A1 Publication Date: 2021-02-11 Application Number: 17/068,396 Filing Date: 2020-10-12 Inventor: Choi, Kang Sik   Assignee: SK hynix Inc.   IPC: H01L29/417 Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
11
US2021036115A1
FIELD-EFFECT TRANSISTOR
Publication/Patent Number: US2021036115A1 Publication Date: 2021-02-04 Application Number: 16/498,349 Filing Date: 2017-09-01 Inventor: Watanabe, Shinsuke   Assignee: Mitsubishi Electric Corporation   IPC: H01L29/417 Abstract: A field effect transistor according to the present invention includes a semiconductor substrate, a plurality of drain electrodes provided on a first surface of the semiconductor substrate and extending in a first direction, an input terminal, an output terminal, and a plurality of metal layers provided in the semiconductor substrate apart from the first surface and extending in a second direction crossing the first direction, in which the plurality of metal layers include a first metal layer and a second metal layer which is longer than the first metal layer and which crosses more drain electrodes than the first metal layer when seen from a direction perpendicular to the first surface, and among the plurality of drain electrodes, those having a smaller length of line from the input terminal to the output terminal are provided with more metal layers directly thereunder.
12
CN112420743A
显示面板和显示面板的制作方法
Substantial Examination
Publication/Patent Number: CN112420743A Publication Date: 2021-02-26 Application Number: 202011228209.5 Filing Date: 2020-11-06 Inventor: 周星宇   Assignee: 深圳市华星光电半导体显示技术有限公司   IPC: H01L27/12 Abstract: 本发明提供一种显示面板和制作方法,显示面板中的有源层包括第一沟道区和第二沟道区,二者间隔设置;掺杂区包括设置在第一沟道区远离第二沟道区的一侧的第一掺杂区,设置在第一沟道区和第二沟道区之间的第二掺杂区和设置在第二沟道区远离第一沟道区的一侧的第三掺杂区;间绝缘层包括与第一掺杂区相对设置的第一通孔,与第二掺杂区相对设置的第二通孔和与第三掺杂区相对设置的第三通孔;第一电极层包括与第一掺杂区电性连接的第一电极,与第二掺杂区电性连接的第二电极,以及与第三掺杂区电性连接的第三电极。该方案提高了显示面板的空间利用率。
13
US10937892B2
Nano multilayer carbon-rich low-k spacer
Publication/Patent Number: US10937892B2 Publication Date: 2021-03-02 Application Number: 16/127,720 Filing Date: 2018-09-11 Inventor: Canaperi, Donald   Conti, Richard A.   Haigh, Jr. Thomas J.   Miller, Eric   Nguyen, Son   Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION   IPC: H01L29/66 Abstract: A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.
14
US2021020743A1
CREATION OF STRESS IN THE CHANNEL OF A NANOSHEET TRANSISTOR
Publication/Patent Number: US2021020743A1 Publication Date: 2021-01-21 Application Number: 16/515,143 Filing Date: 2019-07-18 Inventor: Loubet, Nicolas   Yamashita, Tenko   Audoit, Guillaume   Bernier, Nicolas   Coquand, Remi   Reboh, Shay   Assignee: International Business Machines Corporation   COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES   IPC: H01L29/06 Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.
15
US10930654B2
Semiconductor devices
Publication/Patent Number: US10930654B2 Publication Date: 2021-02-23 Application Number: 16/441,100 Filing Date: 2019-06-14 Inventor: Lim, Hanjin   Park, Kijong   Kim, Younsoo   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L27/108 Abstract: Semiconductor devices are provided. The semiconductor devices may include an active pattern on a substrate. The active pattern may include a first source/drain region and a second source/drain region. The semiconductor devices may also include a bit line electrically connected to the first source/drain region, a first connection electrode electrically connected to the second source/drain region, and a capacitor on the first connection electrode. The capacitor may include a first electrode, a second electrode, and a dielectric pattern between the first and second electrodes. A lower portion of the dielectric pattern may overlap a top surface of the first connection electrode, and the first electrode may extend on an upper portion of a sidewall of the first connection electrode.
16
CN110707158B
阳极边缘浮空的GaN微波二极管及制备方法
Grant
Publication/Patent Number: CN110707158B Publication Date: 2021-01-05 Application Number: 201910976688.X Filing Date: 2019-10-15 Inventor: 张进成   党魁   周弘   张涛   张苇杭   宁静   郝跃   Assignee: 西安电子科技大学   IPC: H01L29/88 Abstract: 本发明公开了一种阳极边缘浮空的GaN微波二极管制备方法,主要解决GaN横向微波二极管电容大,频率响应慢的问题。自下而上包括衬底(1)、GaN缓冲层(2)、GaN沟道层(3)和AlGaN势垒层(4),该沟道层及势垒层上设有圆形凹槽(5),凹槽的外围势垒层上设有环形阴极(6),凹槽的底部、侧壁及凹槽边缘势垒层上方设有阳极(7),且凹槽边缘势垒层上方的阳极与下方势垒层之间设有80‑300nm的间隙,形成长度为0.3‑2μm的部分阳极浮空结构。本发明能大幅降低GaN微波二极管结电容,显著提高器件频率响应,可广泛应用于微波整流和微波限幅。
17
CN112447586A
半导体结构及其形成方法
Substantial Examination
Publication/Patent Number: CN112447586A Publication Date: 2021-03-05 Application Number: 201910833224.3 Filing Date: 2019-09-04 Inventor: 张青淳   Assignee: 中芯国际集成电路制造(上海)有限公司   中芯国际集成电路制造(北京)有限公司   IPC: H01L21/768 Abstract: 一种半导体结构及其形成方法,包括:提供衬底,所述衬底内具有第一开口;在第一开口内形成第一外延层,所述第一外延层内具有第二开口;在所述第二开口的侧壁表面和底部表面形成停止层、以及位于所述停止层表面的第二外延层;在形成所述第二外延层之后,在衬底上形成介质层,所述介质层内具有暴露出所述第二外延层表面的第三开口;刻蚀第三开口底部暴露出的第二外延层直至暴露出所述停止层为止,在所述第二外延层内形成第四开口;采用半导体金属化工艺在第四开口的侧壁表面和底部表面形成接触层。通过所述停止层能够保证刻蚀仅在第二外延层内进行,提高形成第四开口的可控性与精确性,提高形成的半导体结构的性能与良率。
18
CN112510085A
一种IGBT器件及智能功率模块
Substantial Examination
Publication/Patent Number: CN112510085A Publication Date: 2021-03-16 Application Number: 202011360144.X Filing Date: 2020-11-27 Inventor: 兰昊   Assignee: 广东美的白色家电技术创新中心有限公司   美的集团股份有限公司   IPC: H01L29/739 Abstract: 本申请公开了一种IGBT器件及智能功率模块。该IGBT器件包括:沿第一方向依次层叠设置的集电极、漂移区、发射极及栅极,栅极在集电极上的投影位于发射极在集电极上的投影内或部分重叠,以使发射极间隔集电极和栅极。通过这种方式,能够减小IGBT器件的米勒电容,进而降低开关损耗。