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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
CN212785313U
一种多分频十六位二进制加计数器装置
Publication/Patent Number: CN212785313U Publication Date: 2021-03-23 Application Number: 202021995206.X Filing Date: 2020-09-14 Inventor: 吴静   Assignee: 西安培华学院   IPC: H03K21/08 Abstract: 一种多分频十六位二进制加计数器装置,包括定时器,所述定时器输出端分别连接分频器和多倍频混频器,所述分频器的输出端连接多倍频混频器,多倍频混频器输出端连接十六位二进制加计数器。本实用新型通过改变555定时器的输出频率和二进制加计数器的位数,能够实现可控的多分频的、不同范围的二进制加计数,使用范围广泛。
2
US2021013813A1
CONTROLLERS, CONTROL CIRCUITS AND METHODS FOR CONTROLLING INTELLLIGENT DEVICES
Publication/Patent Number: US2021013813A1 Publication Date: 2021-01-14 Application Number: 16/894,377 Filing Date: 2020-06-05 Inventor: Du, Sterling   Ren, Zhimou   Assignee: Beijing Big Moment Technology Co., Ltd   IPC: H02M7/06 Abstract: A controller includes: an input terminal, coupled to a power switch, operable for generating a parameter signal indicating an on/off state of the power switch; a power terminal, coupled to a power source, operable for receiving electric power supplied by the power source to power the controller; an output terminal, coupled to a forwarding module, operable for outputting an indicating signal and a control signal, to enable the forwarding module to read the control signal based on the indicating signal, thus selecting an operating mode of an intelligent device, where both the control signal and the indicating signal are generated by the controller based on the parameter signal.
3
CN106685411B
锁存器电路、双倍数据速率环形计数器及相关器件
Grant
Publication/Patent Number: CN106685411B Publication Date: 2021-01-15 Application Number: 201610446589.7 Filing Date: 2016-06-20 Inventor: 黄元锡   Assignee: 爱思开海力士有限公司   IPC: H03K21/08 Abstract: 公开了锁存器电路、双倍数据速率环形计数器、混合型计数器件、模数转换器件和CMOS图像传感器,锁存器电路接收下一级锁存器电路的负输出作为反馈输入,双倍数据速率环形计数器用来对脉冲时段执行DDR计数并降低切换次数,混合型计数器件通过使用基于锁存器的DDR环形计数器来对低比特位部分进行计数以及通过使用二进制计数器来对高比特位部分进行计数。双倍数据速率环形计数器可以包括环型耦接的多个锁存器。多个锁存器可以包括交替布置的正边沿触发锁存器和负边沿触发锁存器。当前级锁存器根据计数器时钟来接收先前锁存器级的输出以移位至下一锁存器级,接收下一锁存器级的输出来检查至下一锁存器级的数据移位,以及如果检查到数据移位则下降至低电平。
4
CN112290933A
一种电子元件自动计数系统
Substantial Examination
Publication/Patent Number: CN112290933A Publication Date: 2021-01-29 Application Number: 202011235208.3 Filing Date: 2020-11-08 Inventor: 肖旭辉   曹培福   Assignee: 湖南省福晶电子有限公司   IPC: H03K21/18 Abstract: 本发明提供一种电子元件自动计数系统,它包括有红外线发射电路以及红外接收电路,红外线发射电路由电容正反馈式调制荡器电路、40kHz脉冲振荡器和驱动电路组成,其中,电容正反馈式调制振荡器电路由与非门集成电路内部的第一二极管、第二二极管以及第一电阻、第二电阻、第一电容器组成;驱动电路由与非门集成电路内的第五二极管、第六二极管以及第五电阻、第五电阻、第一晶体管、红外发光二极管组成。本发明的电路简单,制作容易,现场使用效果较好。
5
CN112737569A
一种基于九进制进位电路的数字解码电路
Substantial Examination
Publication/Patent Number: CN112737569A Publication Date: 2021-04-30 Application Number: 202011549297.9 Filing Date: 2020-12-24 Inventor: 黄黎杰   罗小华   Assignee: 浙江大学   IPC: H03K29/00 Abstract: 本发明公开了一种基于九进制进位电路的数字解码电路,所述数字解码电路包括:振荡器,用于生成振荡信号;九进制计数电路,对单个DMX512所发送的帧进行计数,得到商和余数;解码算法控制单元,通过得到的商和余数来确定采样脉冲的发送,并得到所需解码的信号;解码器,对得到的信号进行解码,并输出到后续的LED显示装置进行显示。本发明提供的基于九进制进位电路的数字解码电路通过使用余数补偿和补偿间隔分布的方法提高了DMX512解码所需的最小采样周期,减小了误差发生的可能,扩大了DMX512协议在变传输速率环境下的使用范围。
6
US2021064367A1
METHOD AND COMPUTING DEVICE WITH A MULTIPLIER-ACCUMULATOR CIRCUIT
Publication/Patent Number: US2021064367A1 Publication Date: 2021-03-04 Application Number: 16/987,863 Filing Date: 2020-08-07 Inventor: Kim, Sang Joon   Jung, Seungchul   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: G06F9/30 Abstract: Provided is a multiplier-accumulator (MAC) system, circuit, and method. The MAC system includes a MAC circuit, including a plurality of resistors, having respective resistances, a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge, and a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value, wherein the digital value is an accumulation result of the MAC circuit.
7
CN213402976U
基于FPGA的随机性高速脉冲计数系统
Grant
Publication/Patent Number: CN213402976U Publication Date: 2021-06-08 Application Number: 202022467926.5 Filing Date: 2020-10-30 Inventor: 李中举   翟莹莹   刘聪   王聪   王超   聂晶晶   魏文娟   Assignee: 安图实验仪器(郑州)有限公司   IPC: H03K21/02 Abstract: 本实用新型公开了一种基于FPGA的随机性高速脉冲计数系统,包括MCU、FPGA模块、上位机;所述MCU与所述上位机以及所述FPGA模块进行通信,接收上位机计数开始指令,向FPGA模块发送计数开始信号以及读取FPGA模块中的脉冲计数值,并发送给上位机。本实用新型采用FPGA作为计数芯片,在设定时间内对PMT(光电倍增管)或其它脉冲源输出的脉冲信号进行计数,具有计数稳定、实时性强、不会漏计数、稳定可靠。同时使用MCU进行数据处理、发送指令、与上位机保持实时数据交换,实现控制和信息交流的目的。
8
US10983545B2
Voltage control circuit and voltage control method
Publication/Patent Number: US10983545B2 Publication Date: 2021-04-20 Application Number: 15/930,448 Filing Date: 2020-05-13 Inventor: Lin, Chung-chang   Assignee: Realtek Semiconductor Corp.   IPC: H03K3/03 Abstract: A voltage control circuit for controlling an operating voltage of a target circuit, including: a speed detecting circuit, configured to detect an operating speed of the target circuit; and a control circuit, coupled to the speed detecting circuit, configured to generate a voltage control signal according to a difference between the operating speed and a predetermined speed, to a power supply circuit which generates the operating voltage, to control the operating voltage.
9
US2021083677A1
TERMINATION CALIBRATION SCHEME USING A CURRENT MIRROR
Publication/Patent Number: US2021083677A1 Publication Date: 2021-03-18 Application Number: 16/570,334 Filing Date: 2019-09-13 Inventor: Kathuria, Achal   Jayaraman, Pradeep   Assignee: Advanced Micro Devices, Inc.   IPC: H03K21/08 Abstract: Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.
10
US2021050855A1
SIGNAL GENERATION CIRCUIT SYNCHRONIZED WITH A CLOCK SIGNAL AND A SEMICONDUCTOR APPARATUS USING THE SAME
Publication/Patent Number: US2021050855A1 Publication Date: 2021-02-18 Application Number: 16/810,571 Filing Date: 2020-03-05 Inventor: Kim, Young Ouk   Assignee: SK hynix Inc.   IPC: H03K21/08 Abstract: A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals.
11
US10972112B1
50%-duty-cycle consecutive integer frequency divider and phase-locked loop circuit
Publication/Patent Number: US10972112B1 Publication Date: 2021-04-06 Application Number: 16/857,617 Filing Date: 2020-04-24 Inventor: Zhang, Ning   Liu, Yuchun   Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION   IPC: H03L7/183 Abstract: Embodiments described herein relate to a 50%-duty-cycle consecutive integer frequency divider and a phase-locked loop circuit having the frequency divider. The frequency divider includes a consecutive integer frequency divider module having a non-50%-duty-cycle, wherein the module receives a clock signal CLK and an input control signal CB and outputs a consecutive frequency division clock signal CLK1 comprising a non-50% duty cycle; a D flip-flop module for receiving the clock signal CLK and the consecutive frequency division clock signal CLK1 and outputting at least one clock signal CLKx; and a logic OR gate module for receiving the consecutive frequency division clock signal CLK1 and the at least one clock signal CLKx, and outputting an output clock signal CLKout comprising a 50% duty cycle.
12
US11005457B2
PTAT ring oscillator circuit
Publication/Patent Number: US11005457B2 Publication Date: 2021-05-11 Application Number: 16/006,750 Filing Date: 2018-06-12 Inventor: Ahmed, Ramy A.   Hafez, Amr A.   Savoj, Jafar   Assignee: Apple Inc.   IPC: H03K3/03 Abstract: A circuit that produces an output signal having a frequency that is proportional to absolute temperature (PTAT) is disclosed. In one embodiment, the circuit includes a ring oscillator and a bias current circuit coupled thereto. The ring oscillator and the bias current circuit are implemented in close proximity to one another. During operation, the bias current circuit generates a bias current that is provided to the ring oscillator. The amount of bias current generated is dependent upon the temperature of the circuit. In turn, the frequency of an output signal provided by the ring oscillator is dependent on the amount of bias current received from the bias current circuit. Accordingly, the frequency of the ring oscillator output signal is dependent on the temperature of the circuit.
13
CN212811655U
一种小型地理信息数据采集终端
Grant
Publication/Patent Number: CN212811655U Publication Date: 2021-03-26 Application Number: 202021456205.8 Filing Date: 2020-07-22 Inventor: 惠海鹏   叶培   曲仁明   Assignee: 四川方正测量有限公司   IPC: H03K5/01 Abstract: 本实用新型公开了一种小型地理信息数据采集终端,包括视频采集器、信号调理模块、计时模块和处理器;所述视频采集器用于检测流速,其输出端与信号调理模块输入端连接,通过信号调理模块可对视频采集器的输出的脉冲信号进行处理,所述信号调理模块的输出端与处理器和计时模块的输入端连接,计时模块的控制端与处理器连接,其输出端与处理器连接。本实用新型的信号调理模块对视频采集器输出的信号进行调理,将其进行隔离处理,那么可减少外部信号带来的干扰,避免因为测试现场各种干扰因素带来的不确定性,导致后期测试结果出错,且可将视频采集器中输出的不稳定均匀的脉冲信号进行信号整形,以防止电路产生的信号冲击对后期电路造成的损坏。
14
US10944387B2
Programmable delay circuit
Publication/Patent Number: US10944387B2 Publication Date: 2021-03-09 Application Number: 16/896,463 Filing Date: 2020-06-09 Inventor: Bal, Ankur   Tiwari, Jeet Narayan   Assignee: STMicroelectronics International N.V.   IPC: H03K5/133 Abstract: A delay line includes a delay chain, a pulse generator generating a pulse based on a received input signal, and a delay chain control circuit. The delay chain control circuit has a first input receiving the pulse, a second input receiving output from a last element of the delay chain, and a selection input receiving a delayed version of the received input signal. The delay chain control circuit has an output coupled to provide input to a first element of the delay chain in response to the delayed version of the received input signal. An output selection circuit receives outputs from each element of the delay chain, counts assertions of the output of the last element of the delay chain and, in response to the count being equal to a desired count, passes a desired one of the outputs of the elements of the delay chain as output.
15
US11018673B2
Multi-modulus frequency dividers
Publication/Patent Number: US11018673B2 Publication Date: 2021-05-25 Application Number: 16/740,278 Filing Date: 2020-01-10 Inventor: Patel, Pancham R.   Heidari, Esmael   Assignee: Microchip Technology Incorporated   IPC: H03K21/02 Abstract: Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include receiving, at the MMD, an input signal at a first frequency. The method may also include generating, via the MMD, an output signal at a second, lower frequency based on a divisor value. Further, the method may include receiving, at the MMD, an integer value. Moreover, the method may include setting the divisor value equal to the integer value in response to a current state of the MMD matching a common state for the MMD, wherein the MMD is configured to enter the common state regardless of the divisor value.
16
CN112344975A
一种激光编码最小周期识别装置
Substantial Examination
Publication/Patent Number: CN112344975A Publication Date: 2021-02-09 Application Number: 202011353580.4 Filing Date: 2020-11-26 Inventor: 童忠诚   俞峰   张玉发   辛诚   李双刚   程立   孙晓军   Assignee: 中国人民解放军国防科技大学   IPC: G01D5/36 Abstract: 本发明涉及一种激光编码最小周期识别装置,包括接收模块、配置模块、编码识别模块和数据模块;接收模块,用于将激光脉冲进行光电转换、放大以及归一化;配置模块,用于激光脉冲接收时间的录取,并分配激光脉冲接收时间数据至编码识别模块;编码识别模块,用于在接收到激光脉冲接收时间数据样本后,根据时间相关性进行数据样本分类,对分类后的数据样本进行分析找出激光编码的码型特征后,采用模糊决策识别出激光编码最小周期,并对激光编码脉冲和激光干扰脉冲进行回测检验;数据模块,用于存贮和输出激光脉冲接收时间数据、识别过程中产生的中间数据和识别结果数据。本发明解决目前激光编码技术不能满足现代战争对激光半主动制导武器需求的问题。
17
US11025255B2
Signal generation circuit synchronized with a clock signal and a semiconductor apparatus using the same
Publication/Patent Number: US11025255B2 Publication Date: 2021-06-01 Application Number: 16/810,571 Filing Date: 2020-03-05 Inventor: Kim, Young Ouk   Assignee: SK hynix Inc.   IPC: H03K21/00 Abstract: A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals.
18
US2021049307A1
APPARATUS FOR AUTONOMOUS SECURITY AND FUNCTIONAL SAFETY OF CLOCK AND VOLTAGES
Publication/Patent Number: US2021049307A1 Publication Date: 2021-02-18 Application Number: 17/087,414 Filing Date: 2020-11-02 Inventor: Kurd, Nasser   Mosalikanti, Praveen   Hegde, Thripthi   Neidengard, Mark   Grossnickle, Vaughn   Wang, Qi S.   Ramesh, Kandadai   Assignee: Intel Corporation   IPC: G06F21/70 Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
19
US10979058B2
Detection device and detection method
Publication/Patent Number: US10979058B2 Publication Date: 2021-04-13 Application Number: 16/097,658 Filing Date: 2017-04-27 Inventor: Masuda, Makoto   Fujita, Hiroaki   Fujiwara, Tetsuya   Assignee: SONY CORPORATION   IPC: H03L7/085 Abstract: The present technology relates to a first edge detector that detects whether there is an edge of a second clock signal in one cycle of a first clock signal. A second edge detector detects whether there is an edge of the first clock signal in one cycle of the second clock signal. The logic circuit performs a logical operation on a detection result from the first edge detector and a detection result from the second edge detector. The present technology can be applied to a circuit or the like that detects a locked state of a PLL circuit, for example.
20
CN112394387A
一种He-3正比计数器信号拾取电路
Substantial Examination
Publication/Patent Number: CN112394387A Publication Date: 2021-02-23 Application Number: 202011323784.3 Filing Date: 2020-11-23 Inventor: 詹鑫欣   Assignee: 重庆建安仪器有限责任公司   IPC: G01T3/00 Abstract: 本发明公开了一种He‑3正比计数器信号拾取电路,包括正比计数器、前置放大电路、反馈电路、整形电路、滤波电路、电压比较电路、G‑M计数管和微控制器;正比计数器的输出端与前置放大电路的输入端连接;前置放大电路的输出端与整形电路的输入端连接,反馈电路连接在前置放大电路的输入端和输出端之间;整形电路的输出端与滤波电路连接;滤波电路输出端与微控制器的输入端进行连接;微控制器的输出端与电压比较电路的正向输入端连接;电压比较电路的输出端与G‑M计数管连接;G‑M计数管根据电压比较电路的输出数据对中子数量进行计数。本发明能将正比计数器探测的中子数量信号进行有效提取,以便准确获取He‑3中的中子数量。
Total 103 pages