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1
CN112311390A
锁相回路电路
Substantial Examination
Publication/Patent Number: CN112311390A Publication Date: 2021-02-02 Application Number: 201910691231.4 Filing Date: 2019-07-29 Inventor: 陈建文   Assignee: 瑞昱半导体股份有限公司   IPC: H03L7/091 Abstract: 本发明公开一种锁相回路电路,其包括延迟锁相回路及次取样锁相回路。延迟锁相回路用于将第一参考时钟及第二参考时钟锁相于输入时钟,其包括相位修正电路、积分器及第一次取样相位检测电路。次取样锁相回路经配置以预定的锁相回路频率产生输出时钟,且输出时钟锁相于第一参考信号,其包括第二次取样相位检测电路、相位频率检测电路、电压控制振荡器及第一除频器。其中,相位修正电路在工作周期调整模式及延迟锁相回路模式下操作,在工作周期调整模式下,积分器根据第一参考时钟及第二参考时钟产生第一控制信号。在延迟锁相回路模式下,相位修正电路依据第二控制信号调整输入时钟以产生第一参考时钟及第二参考时钟。
2
CN112953522A
高抖动容限的无基准频率检测器
Public
Publication/Patent Number: CN112953522A Publication Date: 2021-06-11 Application Number: 202010897394.0 Filing Date: 2015-12-01 Inventor: 谷亮   曹玉明   雷工   党殷   顾一凡   李洪义   玛曼莎·德什潘德   施守波   段彦   Assignee: 华为技术有限公司   IPC: H03L7/091 Abstract: 一种高抖动容限的无基准频率检测器采样装置用于根据数据信号对时钟信号进行采样,以产生第一采样信号;用于根据延迟信号对所述时钟信号进行采样,以产生第二采样信号;以及耦合到所述采样装置的控制电路,其中,所述控制电路用于根据所述第一采样信号和所述第二采样信号用于调整时钟信号的频率。
3
CN107800427B
时脉数据回复模块
Grant
Publication/Patent Number: CN107800427B Publication Date: 2021-04-06 Application Number: 201610800886.7 Filing Date: 2016-09-05 Inventor: 陈彦中   康文柱   李易霖   Assignee: 创意电子股份有限公司   台湾积体电路制造股份有限公司   IPC: H03L7/091 Abstract: 一种时脉数据回复模块,其包含时脉数据回复回路与展频时脉追踪电路。时脉数据回复回路包含时脉数据回复单元与相位内插单元。时脉数据回复单元依据数据信号产生相位信号,相位内插单元依据相位信号与参考时脉信号产生数据时脉信号与边缘时脉信号。展频时脉追踪电路依据数据信号产生参考时脉信号。时脉数据回复单元更依据数据信号、数据时脉信号以及边缘时脉信号产生相位信号。展频时脉追踪电路与时脉数据回复回路为解耦配置。因此,解耦后的时脉数据回复回路与展频时脉电路得以分别实施不同的相位内插解析度,让其各自达到相位内插解析度的全局最佳解,借以提升相位与频率追踪的精准度与效率,从而符合显示端口对于信号抖动容许度的规定。
4
US10972106B1
Phase and delay compensation circuit and method
Publication/Patent Number: US10972106B1 Publication Date: 2021-04-06 Application Number: 17/091,572 Filing Date: 2020-11-06 Inventor: Chou, Chun-ju   Mu, Yuxiang   Fredenburg, Jeffrey Alan   Assignee: Movellus Circuits, Inc.   IPC: H03L7/081 Abstract: A delay balancing circuit includes a phase detection circuit, a controller, and a delay circuit. The phase detection circuit receives a reference clock signal having a first frequency, and a feedback clock signal derived from an output clock signal. Detection circuitry detects a phase relationship between the reference clock signal and the feedback clock signal. The phase detection circuit generates a detection signal based on the detected phase relationship. The controller operates to sample the detection signal and to generate and pass an update signal to a delay line to update a delay based on the sampled value. The delay circuit receives a third clock signal and applies a delay, based on the update signal, to the third clock signal to generate the output clock signal.
5
CN110768662B
异步数据恢复
Grant
Publication/Patent Number: CN110768662B Publication Date: 2021-03-23 Application Number: 201910663464.3 Filing Date: 2019-07-22 Inventor: A·马丁·马林森   克里斯蒂安·莱特·彼得森   Assignee: 硅谷介入有限公司   IPC: H03L7/091 Abstract: 在本文中描述了一种用于将异步数据恢复到固定时钟域中的装置。已知技术的锁相环(PLL)由修改的正交旋转变压器取代,并且来自旋转变压器的输出重新产生输入异步数据的所选频率分量。该重新产生的数据时钟的过零用于对输入数据流进行采样。该技术的一个优点是它在单个时钟上作为状态机操作,并且不需要诸如相位检测器或VCO的模拟部件。在另一实施方式中,来自输入数据流的样本根据高斯脉冲改变,使得能够将采样率从一个时钟域转换到另一时钟域。
6
CN112468140A
时脉资料回复装置及方法
Substantial Examination
Publication/Patent Number: CN112468140A Publication Date: 2021-03-09 Application Number: 201910864841.X Filing Date: 2019-09-09 Inventor: 张杰雄   张家荣   张毓安   刘晟佑   Assignee: 瑞昱半导体股份有限公司   IPC: H03L7/091 Abstract: 一种时脉资料回复装置,包含:取样电路、储存电路以及判断电路。取样电路包含取样单元,分别根据参考时脉讯号其中之一,对接收资料各进行取样以产生包含取样结果。储存电路包含先进先出储存单元,配置以对应不同时间点,依序储存接收资料的取样结果。判断电路配置以:设定连续P笔接收资料为参考资料样本;在参考资料样本中仅有一个资料转态时,根据其取样数值中的转态点调整取样窗口的起始位置;以及在参考资料样本中有多个资料转态时,根据其取样数值中对应于高态的高态取样数量调整取样窗口的长度。
7
CN112181716A
一种基于延迟锁相环的数据恢复电路
Substantial Examination
Publication/Patent Number: CN112181716A Publication Date: 2021-01-05 Application Number: 201910590047.0 Filing Date: 2019-07-02 Inventor: 邬成   汤小虎   Assignee: 无锡有容微电子有限公司   IPC: G06F11/14 Abstract: 本申请公开了一种基于延迟锁相环的数据恢复电路,包括主环路和补偿支路;主环路包括:相位检测器,用于检测数据信号与时钟信号的相位差并输出对应的检测结果信号和降采样结果信号;与相位检测器连接的电荷泵;与电荷泵连接的储能器;与储能器连接的相位插值器,用于生成与储能器所输出的电压信号对应的时钟调节信号至相位检测器,以便调节时钟信号的相位,令时钟信号与数据信号相位匹配;补偿支路的输入端与相位检测器连接,补偿支路的输出端与电荷泵连接,用于根据降采样结果信号对电荷泵进行电流补偿。本申请既避免了数字器件对电路带宽的限制,又利用补偿支路解决了电荷泵中的电流镜失配问题,有效提高了数据恢复电路的高频抖动容限。
8
US2021083679A1
PHASE-LOCKING APPARATUS AND PHASE-LOCKING METHOD
Publication/Patent Number: US2021083679A1 Publication Date: 2021-03-18 Application Number: 17/105,029 Filing Date: 2020-11-25 Inventor: Yang, Dongsheng   Liu, Fangcheng   Wang, Xiongfei   Assignee: HUAWEI TECHNOLOGIES CO., LTD.   IPC: H03L7/091 Abstract: Embodiments of this application provide a phase-locking apparatus and a phase-locking method. The phase-locking apparatus includes an amplitude adjustment unit, an amplitude and phase detector connected to the amplitude adjustment unit, a first loop filter connected to the amplitude and phase detector, a second loop filter connected to the amplitude and phase detector, a first oscillator connected to the first loop filter, and a second oscillator connected to the second loop filter. The amplitude adjustment unit, the amplitude and phase detector, the first loop filter, and the first oscillator form a loop; and the amplitude and phase detector, the second loop filter, and the second oscillator form another loop. According to the embodiments of this application, a dual-loop structure of the phase-locking apparatus can weaken frequency coupling between a positive-sequence component generated by the phase-locking apparatus and a negative-sequence component generated by the phase-locking apparatus.
9
US11031939B1
Phase detector command propagation between lanes in MCM USR serdes
Publication/Patent Number: US11031939B1 Publication Date: 2021-06-08 Application Number: 16/823,577 Filing Date: 2020-03-19 Inventor: Wolkovitz, Omer   Yanai, Eilon   Assignee: MELLANOX TECHNOLOGIES, LTD.   IPC: H03L7/08 Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate, and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus including at least first and second embedded-clock data lanes. The DCIC includes a clock-data recovery circuit (CDR) and a data sampler. The CDR is configured to restore a data and a clock from the first data lane, and to output phase correction signaling. The data sampler is configured to restore the data from the second data lane by sampling the second data lane at a phase responsive to the phase correction signaling derived from the first data lane.
10
US2021067312A1
CDR CIRCUIT AND RECEIVER OF MULTILEVEL MODULATION METHOD
Publication/Patent Number: US2021067312A1 Publication Date: 2021-03-04 Application Number: 17/004,052 Filing Date: 2020-08-27 Inventor: Kawasoe, Nobuaki   Yoshizawa, Yoshiharu   Yamazaki, Manabu   Assignee: FUJITSU LIMITED   IPC: H04L7/02 Abstract: A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.
11
CN112640311A
利用宽频率采集的亚采样锁相环路(SSPLL)
Public
Publication/Patent Number: CN112640311A Publication Date: 2021-04-09 Application Number: 201980056147.3 Filing Date: 2019-07-24 Inventor: S·昆杜   S·佩勒拉诺   A·阿格拉沃尔   Assignee: 苹果公司   IPC: H03L7/091 Abstract: 本发明公开了一种具有锁频环路(FLL)和锁相环路(PLL)的亚采样器锁相环路(SSPLL)系统。该FLL被配置为检测锁相环路(PLL)输出信号和参考频率之间的频率变化,在检测到该频率变化时自动生成脉冲校正信号,并且将该脉冲校正信号施加到电压控制振荡器(VCO)控制电压。该PLL被配置为基于该VCO控制电压生成该PLL输出信号。
12
US2021044299A1
METHOD AND APPARATUS FOR STOCHASTIC RING OSCILLATOR TIME-TO-DIGITAL CONVERTER WITH INTERLEAVED LOOP COUNTERS
Publication/Patent Number: US2021044299A1 Publication Date: 2021-02-11 Application Number: 16/977,627 Filing Date: 2018-03-30 Inventor: Tertinek, Stefan   Assignee: Apple Inc.   IPC: H03L7/099 Abstract: A method and apparatus for generating a digital signal indicating a time between a start and a stop signal, including a short inverter ring operable to generate a clock signal. The clock signal is provided to a time-interleaved counter array that distributes the clock signal on a plurality of clock outputs as interleaved clock signals. Each interleaved clock signal is provided to a counter that counts a partial count value. The partial count values are combined to obtain a total count value as the digital signal indicating the time. A fine resolution signal is obtained from a chain of stochastic flip flops connected to outputs of the inverters in the short inverter ring. Multiple clock signal outputs of the inverter ring may be provided to multiple interleaved counters.
13
US2021075431A1
FREQUENCY LOCKED LOOP, ELECTRONIC DEVICE, AND FREQUENCY GENERATION METHOD
Publication/Patent Number: US2021075431A1 Publication Date: 2021-03-11 Application Number: 16/633,287 Filing Date: 2019-01-02 Inventor: Wei, Xiangye   Xlu, Liming   Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.   BOE TECHNOLOGY GROUP CO., LTD.   IPC: H03L7/099 Abstract: A frequency locked loop, an electronic device, and a frequency generation method are provided. The frequency locked loop includes: a control circuit, configured to judge a size relationship between an input frequency and a feedback frequency to obtain a control signal, and determine a frequency control word according to the control signal, in which the control signal includes a first sub-control signal and a second sub-control signal, the control circuit is configured to generate the first sub-control signal in a case where the input frequency is greater than the feedback frequency, and the control circuit is configured to generate the second sub-control signal different from the first sub-control signal in a case where the input frequency is less than the feedback frequency; and a digital control oscillation circuit, configured to generate and output an output signal having a target frequency according to the frequency control word.
14
US10979059B1
Successive approximation register analog to digital converter based phase-locked loop with programmable range
Publication/Patent Number: US10979059B1 Publication Date: 2021-04-13 Application Number: 17/079,805 Filing Date: 2020-10-26 Inventor: Shalmani, Soheyl Ziabakhsh   Aouini, Sadok   Mikkelsen, Matthew   Beshara, Hazem   Wen, Tingjun   Honarparvar, Mohammad   Ben-hamida, Naim   Assignee: Ciena Corporation   IPC: H03L7/093 Abstract: Described herein are apparatus and methods for a successive approximation register (SAR) analog-to-digital (ADC) based phase-locked loop (PLL) with programmable range. A multi-bit digital phase locked loop includes a multi-bit phase frequency detector configured to output a multi-bit error signal based on a reference clock, a feedback clock sampled using the reference clock, and a threshold voltage, a multi-bit digital low pass filter configured to apply a variable gain to the multi-bit error signal, a current steered digital-to-analog converter configured to generate a control current based on a gain applied multi-bit error signal and multi-bit digital phase locked loop control parameters, a controlled oscillator configured to adjust a frequency of the controlled oscillator based on the control current to generate an output clock, the feedback clock being based on the output clock, and a programmable edge time controller configured to adjust a slope of an edge of the feedback clock.
15
US11012080B2
Frequency locked loop, electronic device, and frequency generation method
Publication/Patent Number: US11012080B2 Publication Date: 2021-05-18 Application Number: 16/633,287 Filing Date: 2019-01-02 Inventor: Wei, Xiangye   Xiu, Liming   Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.   BOE TECHNOLOGY GROUP CO., LTD.   IPC: H03L7/099 Abstract: A frequency locked loop, an electronic device, and a frequency generation method are provided. The frequency locked loop includes: a control circuit, configured to judge a size relationship between an input frequency and a feedback frequency to obtain a control signal, and determine a frequency control word according to the control signal, in which the control signal includes a first sub-control signal and a second sub-control signal, the control circuit is configured to generate the first sub-control signal in a case where the input frequency is greater than the feedback frequency, and the control circuit is configured to generate the second sub-control signal different from the first sub-control signal in a case where the input frequency is less than the feedback frequency; and a digital control oscillation circuit, configured to generate and output an output signal having a target frequency according to the frequency control word.
16
US10897260B2
Systems and methods for performing phase error correction
Publication/Patent Number: US10897260B2 Publication Date: 2021-01-19 Application Number: 15/366,820 Filing Date: 2016-12-01 Inventor: Liu, Zhao   Yan, Wen   Xiong, Zhenhua   Yuan, Liang   Han, Hongzheng   Lu, Yuan   Assignee: Marvell Asia Pte, Ltd.   IPC: H03L7/099 Abstract: Systems and methods for performing phase error correction are provided. A reference clock signal and a target clock signal are received. A first value is generated based on a first amount of time between a first edge of the reference clock signal and a corresponding first edge of the target clock signal. A phase of the target clock signal is adjusted a first time based on a given amount computed using the first value. After the phase of the target clock signal is adjusted, a second value is generated based on a second amount of time between a second edge of the reference clock signal and a corresponding second edge of the target clock signal. The phase of the target clock signal is adjusted a second time based on the given amount, the first value, and the second value.
17
CN107852153B
延迟锁相环
Grant Assignment
Publication/Patent Number: CN107852153B Publication Date: 2021-04-27 Application Number: 201680043099.0 Filing Date: 2016-06-02 Inventor: 张涛   刘雪梅   王晖   Assignee: 马维尔亚洲私人有限公司   IPC: H03K5/06 Abstract: 一种可编程延迟线包括:延迟级,响应模拟控制信号且响应一个或多个数字控制信号。延迟级生成输出信号,输出信号相对于输入信号延迟一延迟量。延迟量通过模拟控制信号的值以及数字控制信号的一个或多个值来控制。一种用于控制延迟锁相环电路的方法包括:向延迟锁相环电路的可编程延迟线提供一个或多个数字信号;以及向可编程延迟线提供模拟信号。由可编程延迟线产生的延迟的第一部分对应于一个或多个数字信号的值。由可编程延迟线产生的延迟的第二部分对应于模拟信号的值。
18
US2021021272A1
TECHNIQUES FOR ADRESSING PHASE NOISE AND PHASE LOCK LOOP PERFORMANCE
Publication/Patent Number: US2021021272A1 Publication Date: 2021-01-21 Application Number: 16/766,921 Filing Date: 2018-03-30 Inventor: Karandikar, Niranjan   Ballantyne, Wayne   Chance, Gregory   Hughes, Simon   Schwartz, Daniel   Tanzi, Nebil   Assignee: Intel IP Corporation   IPC: H03L7/099 Abstract: Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.
19
CN112332835A
实时检测数字相控阵时频信号故障及其恢复处理方法
Substantial Examination
Publication/Patent Number: CN112332835A Publication Date: 2021-02-05 Application Number: 202011190626.5 Filing Date: 2020-10-30 Inventor: 张帆   曾富华   Assignee: 西南电子技术研究所(中国电子科技集团公司第十研究所)   IPC: H03L7/08 Abstract: 本发明提出的一种实时检测数字相控阵时频信号故障及其恢复处理方法,旨在提供一种虚警率小,稳健可靠的处理方法。本发明通过下述技术方案实现:在时钟故障检测中,锁相环锁定指示累计积分处理判断时钟真实锁定状况,通过时钟锁定—失锁—再锁定判决机制,决定是否触发系统重同步操作;在同步信号故障检测中,通过测量时钟计数器分频得到同步信号与外同步信号相位差值,通过多次测量相位值找到跳变点,并对其进行中值滤波,剔除野值后得到的跳变点加半个时钟周期对应的相位值,与上一次设置的最佳采样对应相位值进行比较,当二者不等则认为同步信号出现过故障,同步信号判决模块输出重同步触发信号触发重同步操作,重新恢复数字相控阵系统正常工作。
20
US10892763B1
Second-order clock recovery using three feedback paths
Publication/Patent Number: US10892763B1 Publication Date: 2021-01-12 Application Number: 16/874,261 Filing Date: 2020-05-14 Inventor: Hidaka, Yasuo   Sun, Junqing (phil)   Assignee: Credo Technology Group Limited   IPC: H03L7/08 Abstract: An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop that provides a clock signal; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal; a timing error estimator that produces a timing error signal; a first feedback path coupling the timing error signal to the phase interpolator to minimize a phase component of the estimated timing error; a second feedback path coupling the timing error signal to the phase interpolator; and a third feedback path coupling the timing error signal to the fractional-N phase lock loop, the second and third feedback paths minimizing a frequency offset component of the estimated timing error.
Total 169 pages