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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 CN111327325A
半导体器件和系统
Public
Publication/Patent Number: CN111327325A Publication Date: 2020-06-23 Application Number: 201911156693.2 Filing Date: 2019-11-22 Inventor: 饭冢洋一   森下玄   Assignee: 瑞萨电子株式会社   IPC: H03M1/56 Abstract: 本文描述了半导体器件和系统。本发明提供一种具有能够加速的积分型A/D转换器的半导体器件。该半导体器件包括:用于发送低位计数器信号JC的约翰逊计数器18;用于通过低位计数器信号JC和低位锁存信号14来输出低位锁存结果信号的低位锁存电路11;用于通过低位锁存信号14来输出高位锁存信号15的确定电路12;用于发送高位计数器信号GR的二进制格雷转换器电路20;以及用于通过高位计数器信号GR和高位锁存信号15来输出高位锁存结果信号的高位锁存电路13。
2 CN111201715A
时域A/D转换器组以及使用该时域A/D转换器的传感器装置
Under Examination
Publication/Patent Number: CN111201715A Publication Date: 2020-05-26 Application Number: 201880065606.X Filing Date: 2018-07-30 Inventor: 松泽昭   野原正也   Assignee: 科技创意有限公司   IPC: H03M1/56 Abstract: 构成根据本公开实施方式的时域A/D转换器组的各个A/D转换器与参考信号发生电路连接,该参考信号发生电路产生在满量程范围内进行扫描的第一参考信号及周期性地在被限定的电压范围内多次扫描的第二参考信号,该A/D转换器包括:参考电压选择电路,该参考电压选择电路对作为参考信号发生电路的输出的第一或者第二参考信号进行切换;比较器,用于比较由参考电压选择电路选择出的第一或者第二参考信号与输入信号;内部A/D转换器,用于利用来自比较器的比较输出信号进行A/D转换;和累积加减法器,用于在第二参考信号被选择时输出对通过A/D转换得到的A/D转换值进行平均得到的信号。
3 CN111541453A
时域A/D转换器组
Under Examination
Publication/Patent Number: CN111541453A Publication Date: 2020-08-14 Application Number: 202010359181.2 Filing Date: 2018-07-30 Inventor: 松泽昭   野原正也   Assignee: 科技创意有限公司   IPC: H03M1/56 Abstract: 本公开提供一种包括多个A/D转换模块的时域A/D转换器组,每个A/D转换模块包括:延迟锁定环电路,其将向集成电路提供时钟的主时钟作为输入,对主时钟分频,输出不同时序的多相时钟;逻辑电路,其根据多相时钟合成与格雷码对应的多个时钟;彼此空间相邻的多个A/D转换器;延迟锁定环电路和逻辑电路分散布置在集成电路中,将多个时钟提供给同一A/D转换模块的多个A/D转换器;每个A/D转换器包括将输入信号和参考电压进行比较来生成比较输出信号的比较器和内部A/D转换器,内部A/D转换器包括根据比较输出信号提供的时序保持多相时钟的逻辑状态的锁存器和对多个时钟中最大宽度的时钟计数并根据比较器输出停止计数的计数器。
4 EP3602790A1
LOW POWER ANALOG-TO-DIGITAL CONVERTER
Publication/Patent Number: EP3602790A1 Publication Date: 2020-02-05 Application Number: 18716770.5 Filing Date: 2018-03-21 Inventor: Boemler, Christian M.   Assignee: Raytheon Company   IPC: H03M1/08
5 JPWO2018163895A1
固体撮像装置、およびそれを用いるカメラシステム
Publication/Patent Number: JPWO2018163895A1 Publication Date: 2020-01-09 Application Number: 2019504486 Filing Date: 2018-02-27 Inventor: 一柳, 大   西村, 佳壽子   阿部, 豊   樋口, 真浩   藤中, 洋   Assignee: パナソニックIPマネジメント株式会社   IPC: H03M1/56 Abstract: 固体撮像装置は、列毎のAD変換部(40)を備え、AD変換部(40)は、第1の比較器(404)を用いて、アナログ信号の電位が含まれる範囲を二分探索により第1の電位(V1)と第2の電位(V2)の差分に応じた電位の範囲に絞り込み、更に、二分探索の結果に基づいてデジタル信号の上位側部分である第1のデジタル信号を生成する第1のAD変換を行い、ランプ信号(Vramp)および二分探索の結果に基づいて、第2の比較器(405)の出力が反転するまでの時間を計測することで、デジタル信号の残りの下位側部分である第2のデジタル信号を生成する第2のAD変換を行う。
6 CN111434106A
固体摄像装置和AB级超源跟随器
Public
Publication/Patent Number: CN111434106A Publication Date: 2020-07-17 Application Number: 201880073775.8 Filing Date: 2018-11-06 Inventor: 樋口真浩   Assignee: 松下半导体解决方案株式会社   IPC: H04N5/378 Abstract: 通过将驱动固体摄像装置的列并列单斜率型ADC的参照斜坡信号的超源跟随器的输出缓冲器设为AB级反馈结构,从而使放大晶体管的漏极电压的上限不被反馈可变电流源的栅极源极间电压限制,所述AB级反馈结构以放大器放大流过放大晶体管的电流变动的信号来控制反馈可变电流源。
7 US2020169265A1
ANALOG-TO-DIGITAL CONVERSION DEVICE, PHOTOELECTRIC CONVERSION DEVICE, PHOTOELECTRIC CONVERSION SYSTEM, AND MOVABLE OBJECT
Publication/Patent Number: US2020169265A1 Publication Date: 2020-05-28 Application Number: 16/682,677 Filing Date: 2019-11-13 Inventor: Saito, Kazuhiro   Kobayashi, Hideo   Itano, Tetsuya   Assignee: CANON KABUSHIKI KAISHA   IPC: H03M1/56 Abstract: An analog-to-digital conversion device of the embodiment includes a comparator and a logic circuit including a switch unit and a logic gate unit that receives a signal output from a comparator. The logic gate unit and the switch unit are connected to each other in series between a power supply node and a ground node.
8 US2020137340A1
ANALOG TO DIGITAL CONVERTING CIRCUIT AND AN OPERATION METHOD THEREOF
Publication/Patent Number: US2020137340A1 Publication Date: 2020-04-30 Application Number: 16/703,313 Filing Date: 2019-12-04 Inventor: Kim, Yunhong   Kim, Kyung-min   Chae, Heesung   Assignee: Samsung Electronics Co., Ltd.   IPC: H04N5/378 Abstract: An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal “N” times, and outputs an extended signal, wherein the “N” is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.
9 US2020044660A1
ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION
Publication/Patent Number: US2020044660A1 Publication Date: 2020-02-06 Application Number: 16/494,829 Filing Date: 2018-03-16 Inventor: Xhakoni, Adi   Ruythooren, Koen   Assignee: ams AG   IPC: H03M1/06 Abstract: In one embodiment an analog-to-digital converter circuit has an input for receiving a first analog signal level and a second analog signal level, a ramp generator adapted to provide a ramp signal, a comparison unit coupled to the input and the ramp generator, a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, and an output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level. Therein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and the falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal.
10 CN111418203A
固体摄像装置和摄像系统
Public
Publication/Patent Number: CN111418203A Publication Date: 2020-07-14 Application Number: 201880073975.3 Filing Date: 2018-11-06 Inventor: 东阳介   角谷范彦   Assignee: 松下半导体解决方案株式会社   IPC: H04N5/378 Abstract: 固体摄像装置(1000)具备:第一转换部,将表示像素值的模拟信号转换为数字信号的高位比特;以及第二转换部,将模拟信号转换为数字信号的低位比特,第二转换部具备:第一锁存电路,在第一转换部中的向高位比特的转换定时,将相互具有相位差的多个时钟信号作为相位信息进行锁存;转换电路,将相位信息转换为二进制值,由此生成数字信号的低位比特;加法器(330);以及第二锁存电路(340),对加法器的相加结果进行锁存,加法器(330)将由转换电路(320)转换的二进制值和被第二锁存电路锁存的值相加。
11 WO2020026610A1
SOLID-STATE IMAGING DEVICE, CODE CONVERSION DEVICE, CODE CONVERSION METHOD, AND PROGRAM
Publication/Patent Number: WO2020026610A1 Publication Date: 2020-02-06 Application Number: 2019023732 Filing Date: 2019-06-14 Inventor: Katayama, Isao   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H04N5/378 Abstract: The present invention enables a code to be utilized, in which the Hamming distance in an arbitrary code length is always 1. This solid-state imaging device (1) is provided with: a plurality of pixels (121), a comparator (215) which compares a pixel signal with a reference signal; and a counter (207) which counts a time until levels of the pixel signal and the reference signal are the same. The counter includes: a first calculation unit (233) which calculates a comparison value by right-shifting, by one bit, a maximum value that represents, with an n-bit binary code, a number obtained by subtracting 1 from an even code length of 2 to 2n; a first selection unit (239) which outputs, as a third value, any one among a first value and a second value obtained by subtracting the first value from the maximum value on the basis of a comparison result between the comparison value and the first value that is any one from 0 to the maximum value represented with the n-bit binary code; and a second calculation unit (241) which converts the third value from the n-bit binary code to an n-bit Gray code, and generates, on the basis of the comparison result, a pseudo code by setting 0 or 1 to the most significant bit of the Gray code.
12 US10587832B2
Analog to digital converting circuit and an operation method thereof
Publication/Patent Number: US10587832B2 Publication Date: 2020-03-10 Application Number: 15/996,996 Filing Date: 2018-06-04 Inventor: Kim, Yunhong   Kim, Kyung-min   Chae, Heesung   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H04N5/378 Abstract: An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal “N” times, and outputs an extended signal, wherein the “N” is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.
13 US10666281B2
Method, device and system for analog-to-digital conversion
Publication/Patent Number: US10666281B2 Publication Date: 2020-05-26 Application Number: 16/386,699 Filing Date: 2019-04-17 Inventor: Pernull, Martin   Bogner, Peter   Assignee: INFINEON TECHNOLOGIES AG   IPC: H03M1/10 Abstract: In accordance with an embodiment, a method for calibrating at least two analog-to-digital converters includes feeding an analog predefined signal to the at least two analog-to-digital converters; converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on a received clock signal; and adapting a converter-specific time delay based on the at least two converter-associated digital values.
14 JP2020005245A
撮像装置、撮像システム及び信号処理装置
Publication/Patent Number: JP2020005245A Publication Date: 2020-01-09 Application Number: 2019018616 Filing Date: 2019-02-05 Inventor: Assignee: IPC: H04N5/378 Abstract: 【課題】デジタルデータの水平転送動作に伴う消費電流の変化に起因した画質劣化を低減しうる撮像装置を提供する。【解決手段】複数の行及び複数の列を構成するように配され、各々が入射光の光量に応じた信号を出力する複数の画素と、複数の列に対応して設けられ、対応する列に配された画素から出力される信号をA/D変換するA/D変換部を各々が有する複数の列信号処理部と、複数の列に対応して設けられ、対応する列の列信号処理部が出力するデジタルデータを保持するメモリを各々が有する複数のメモリ部と、複数のメモリ部の各々が保持するデジタルデータを順次、共通出力線に出力する転送部と、共通出力線に続けて出力される第1のデジタルデータ及び第2のデジタルデータのうちの一方のビットの値を反転するビット値反転部とを有する。【選択図】図2
15 US2020275045A1
SOLID-STATE IMAGING DEVICE AND IMAGING SYSTEM
Publication/Patent Number: US2020275045A1 Publication Date: 2020-08-27 Application Number: 15/930,152 Filing Date: 2020-05-12 Inventor: Higashi, Yosuke   Sumitani, Norihiko   Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.   IPC: H04N5/3745 Abstract: A solid-state imaging device includes a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal, and a second converter which converts the analog signal to a lower bit of the digital signal. The second converter includes a first latch circuit which latches, as phase information, a plurality of clock signals having different phases upon conversion to the upper bit in the first converter, a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value, and an adder, and a second latch circuit which latches an addition result of the adder. The adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.
16 WO2020031439A1
SOLID-STATE IMAGING ELEMENT, IMAGING DEVICE, AND METHOD FOR CONTROLLING SOLID-STATE IMAGING ELEMENT
Publication/Patent Number: WO2020031439A1 Publication Date: 2020-02-13 Application Number: 2019017845 Filing Date: 2019-04-26 Inventor: Segami, Masahiro   Oosako, Youhei   Yamashita, Tomonori   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H04N5/378 Abstract: A solid-state imaging element for performing AD conversion using a reference signal, wherein the power consumption of a circuit that generates the reference signal is reduced. A pixel unit outputs a pixel signal based on the luminous energy of incident light. A reference signal supply unit generates a first reference signal and a second reference signal. A comparison unit includes first differential pair transistors to which a signal based on the pixel signal and the first reference signal are inputted, and second differential pair transistors to which the second reference signal is inputted. A counter unit counts a count value on the basis of a signal from the comparison unit.
17 CN106576149B
固态摄像元件和电子装置
Valid
Title (English): Solid-state camera elements and electronic devices
Publication/Patent Number: CN106576149B Publication Date: 2020-01-14 Application Number: 201580043015.9 Filing Date: 2015-08-06 Inventor: 阿比留隆浩   久松康秋   永田忠史   Assignee: 索尼公司   IPC: H04N5/378 Abstract: 本发明涉及能够高速地执行增益转换的固态摄像元件和电子装置。斜波生成电路包括与所需增益的类型(例如,两种类型,即,低增益和高增益)相对应的数量的采样保持电路和斜波生成DAC。两个采样保持电路可以分别保持不同增益的增益DAC输出电压。由此,能够通过斜波选择信号实现至保持所需增益电压的斜波生成DAC的切换。本发明可例如应用于用于成像装置的CMOS固态图像传感器。
18 US10530380B2
Massively parallel three dimensional per pixel single slope analog to digital converter
Publication/Patent Number: US10530380B2 Publication Date: 2020-01-07 Application Number: 15/964,511 Filing Date: 2018-04-27 Inventor: Beuville, Eric J.   Kuiken, Matthew T.   Cantrell, Joshua J.   Massie, Mark A.   Assignee: RAYTHEON COMPANY   IPC: H03M1/14 Abstract: An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through a silicon via.
19 US2020260037A1
METHODS OF OPERATING IMAGE SENSORS AND IMAGE SENSORS PERFORMING THE SAME
Publication/Patent Number: US2020260037A1 Publication Date: 2020-08-13 Application Number: 16/663,770 Filing Date: 2019-10-25 Inventor: Cho, Kyu-ik   Assignee: Samsung Electronics Co., Ltd.   IPC: H04N5/378 Abstract: A method of operating an image sensor includes generating an analog pixel signal, including a reset component and an image component, based on incident light received by a pixel in the image sensor. Operations are performed to repeatedly sample the reset component of the analog pixel signal using a ramp signal, during a first time interval, and then repeatedly sample the image component of the analog pixel signal using the ramp signal, during a second time interval subsequent to the first time interval. A digital signal corresponding to an effective image component of the incident light is then generated. This digital signal is based on the repeatedly sampled reset component of the analog pixel signal and the repeatedly sampled image component of the analog pixel signal. In addition, during both the first and second time intervals, the ramp signal decreases in magnitude and increases in magnitude.
20 US10659056B1
Gray code counting signal distribution system
Publication/Patent Number: US10659056B1 Publication Date: 2020-05-19 Application Number: 16/440,279 Filing Date: 2019-06-13 Inventor: Sakurai, Satoshi   Ebihara, Hiroaki   Assignee: OmniVision Technologies, Inc.   IPC: H03K23/00 Abstract: A counter distribution system includes an N bit counter to receive a first counting clock to generate a plurality of data bits including lower data bits on lower data bit lines and upper data bits on upper data bit lines. The upper data bits include at least one redundant bit to provide error correction for the counter distribution system. A plurality of latches is coupled to the N bit counter. Each one of the lower data bit lines and each one of the upper data bit lines is coupled to at least one of the latches. The latches are arranged into a plurality of groupings of latches. Each grouping of latches is coupled to a respective latch enable signal. Each latch in each grouping of latches is coupled to latch a respective one of the plurality of data bits in response to the respective latch enable signal.