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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US2018329708A1
MULTI-NULLIFICATION
Publication/Patent Number: US2018329708A1 Publication Date: 2018-11-15 Application Number: 16/042,957 Filing Date: 2018-07-23 Inventor: Burger, Douglas C.   Smith, Aaron L.   Assignee: Microsoft Technology Licensing, LLC   IPC: G06F9/30 Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.
2 US2018357129A1
VIRTUAL MACHINE BACKUP
Publication/Patent Number: US2018357129A1 Publication Date: 2018-12-13 Application Number: 16/108,236 Filing Date: 2018-08-22 Inventor: Guthrie, Guy Lynn   Nayar, Naresh   North, Geraint   Shen, Hugh   Starke, William   Williams, Phillip   Assignee: International Business Machines Corporation   IPC: G06F11/14 Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
3 US2018357131A1
VIRTUAL MACHINE BACKUP
Publication/Patent Number: US2018357131A1 Publication Date: 2018-12-13 Application Number: 16/108,583 Filing Date: 2018-08-22 Inventor: Guthrie, Guy Lynn   Nayar, Naresh   North, Geraint   Shen, Hugh   Starke, William   Williams, Phillip   Assignee: International Business Machines Corporation   IPC: G06F11/14 Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
4 US2018348995A1
MULTI-DISPLAY CONTROL
Publication/Patent Number: US2018348995A1 Publication Date: 2018-12-06 Application Number: 16/101,793 Filing Date: 2018-08-13 Inventor: Gimpl, Martin   De, Paz Alexander   Sirpal, Sanjiv   Assignee: Z124   IPC: G06F3/0481 Abstract: A dual-screen user device and methods for controlling data displayed thereby are disclosed. Specifically, the data displayed by the multiple screens of the dual-screen user device is conditioned upon the type of user gesture or combination of user gestures detected. The display controls described herein can correlate user inputs received in a gesture capture region to one or more display actions, which may include maximization, minimization, or reformatting instructions.
5 US2018246842A1
Accessory Device Architecture
Publication/Patent Number: US2018246842A1 Publication Date: 2018-08-30 Application Number: 15/960,439 Filing Date: 2018-04-23 Inventor: Drasnin, Sharon   Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC   IPC: G06F13/42 Abstract: An accessory device architecture is described. In one or more implementations, data is received from an accessory device at an integrated circuit of a computing device, the data usable to enumerate functionality of the accessory device for operation as part of a computing device that includes the integrated circuit. The data is passed by the integrated circuit to an operating system executed on processor of the computing device to enumerate the functionality of the accessory device as part of the integrated circuit.
6 US2018357167A1
CACHED VOLUMES AT STORAGE GATEWAYS
Publication/Patent Number: US2018357167A1 Publication Date: 2018-12-13 Application Number: 16/003,956 Filing Date: 2018-06-08 Inventor: Salyers, David Carl   Vincent, Pradeep   Khetrapal, Ankur   Patiejunas, Kestutis   Assignee: Amazon Technologies, Inc.   IPC: G06F12/0802 Abstract: Methods and apparatus for supporting cached volumes at storage gateways are disclosed. A storage gateway appliance is configured to cache at least a portion of a storage object of a remote storage service at local storage devices. In response to a client's write request, directed to at least a portion of a data chunk of the storage object, the appliance stores a data modification indicated in the write request at a storage device, and asynchronously uploads the modification to the storage service. In response to a client's read request, directed to a different portion of the data chunk, the appliance downloads the requested data from the storage service to the storage device, and provides the requested data to the client.
7 US2018357448A1
SECURE MASTER AND SECURE GUEST ENDPOINT SECURITY FIREWALL
Publication/Patent Number: US2018357448A1 Publication Date: 2018-12-13 Application Number: 16/047,298 Filing Date: 2018-07-27 Inventor: Anderson, Timothy D.   Zbiciak, Joseph R. M.   Pierson, Matthew D.   Chirca, Kai   Assignee: TEXAS INSTRUMENTS INCORPORATED   IPC: G06F21/78 Abstract: Disclosed embodiments relate to a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.
8 US2018239599A1
Wrapping Unmanaged Applications on a Mobile Device
Publication/Patent Number: US2018239599A1 Publication Date: 2018-08-23 Application Number: 15/957,642 Filing Date: 2018-04-19 Inventor: Aravindakshan, Vipin   Barton, Gary   Lang, Zhongmin   Walker, James   Assignee: Citrix Systems, Inc.   IPC: G06F21/53 Abstract: Methods and systems are disclosed for providing approaches to generating managed applications from unmanaged applications on a mobile device. The methods and systems may include storing, by a mobile device in a memory of the mobile device, one or more unmanaged applications each comprising a corresponding application bundle and decoding, by the mobile device, the retrieved application bundle corresponding to the first unmanaged application. The methods and systems may also include modifying, by the mobile device, the decoded application bundle corresponding to the first unmanaged application by adding a set of one or more policy-based control instructions, compiling, by the mobile device, the modified application bundle to generate a first managed application, the first managed application being configured to operate in accordance with the set of one or more policy-based control instructions, and providing, by the mobile device, the first managed application.
9 US2018365122A1
STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING
Publication/Patent Number: US2018365122A1 Publication Date: 2018-12-20 Application Number: 16/112,996 Filing Date: 2018-08-27 Inventor: Zbiciak, Joseph   Anderson, Timothy D.   Bui, Duc   Chirca, Kai   Assignee: TEXAS INSTRUMENTS INCORPORATED   IPC: G06F11/30 Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.
10 US2018067762A1
MULTITHREADED TRANSACTIONS
Publication/Patent Number: US2018067762A1 Publication Date: 2018-03-08 Application Number: 15/807,614 Filing Date: 2017-11-09 Inventor: Shum, Chung-lung K.   Schwarz, Eric M.   Salapura, Valentina   Gschwind, Michael K.   Busaba, Fadi Y.   Assignee: International Business Machines Corporation   IPC: G06F9/48 Abstract: Embodiments relate to multithreaded transactions. An aspect includes assigning a same transaction identifier (ID) corresponding to the multithreaded transaction to a plurality of threads of the multithreaded transaction, wherein the plurality of threads execute the multithreaded transaction in parallel. Another aspect includes determining one or more memory areas that are owned by the multithreaded transaction. Another aspect includes receiving a memory access request from a requester that is directed to a memory area that is owned by the transaction. Yet another aspect includes based on determining that the requester has a transaction ID that matches the transaction ID of the multithreaded transaction, performing the memory access request without aborting the multithreaded transaction.
11 US2018081816A1
MEMORY MANAGEMENT SUPPORTING HUGE PAGES
Publication/Patent Number: US2018081816A1 Publication Date: 2018-03-22 Application Number: 15/273,433 Filing Date: 2016-09-22 Inventor: Sprinkle, Robert S.   Johnson, Christopher Lyle   Borchers, Albert   Coburn, Joel Dylan   Assignee: Google Inc.   IPC: G06F12/1027 Abstract: Methods, systems, and apparatus for receiving a request to access, from a main memory, data contained in a first portion of a first page of data, the first page of data having a first page size; initiating a page fault based on determining that the first page of data is not stored in the main memory; allocating a portion of the main memory equivalent to the first page size; transferring the first portion of the first page of data from the secondary memory to the allocated portion of the main memory without transferring the entire first page of data; and updating a first page table entry associated with the first portion of the first page of data to point to a location of the allocated portion of the main memory to which the first portion of the first page of data is transferred.
12 US2018246802A1
BACKWARD COMPATIBILITY TESTING OF SOFTWARE IN A MODE THAT DISRUPTS TIMING
Publication/Patent Number: US2018246802A1 Publication Date: 2018-08-30 Application Number: 15/967,246 Filing Date: 2018-04-30 Inventor: Cerny, Mark Evan   Simpson, David   Assignee: Sony Interactive Entertainment LLC   IPC: G06F11/36 Abstract: A device may be run in a timing testing mode in which the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors. The application may be tested for errors while the device is running in the timing testing mode
13 US2018046585A1
TIMELY ADDRESS SPACE RANDOMIZATION
Publication/Patent Number: US2018046585A1 Publication Date: 2018-02-15 Application Number: 15/234,028 Filing Date: 2016-08-11 Inventor: Okhravi, Hamed   Hobson, Thomas R.   Bigelow, David O.   Rudd, Robert   Streilein, William W.   Assignee: Massachusetts Institute of Technology   IPC: G06F21/54 Abstract: A method for timely address space randomize includes loading a code region from a program binary to a first location within the address space, detecting, during execution of the program, an output-input call pair from the program and, in response to detecting the output-input call pair from the program: selecting a second location within the address space to move the code region to, determining memory locations of one or more references to the code region, updating the values of the references in memory based on the second location and using annotation information within the program binary, and moving the code region to the second location within the address space.
14 US2018121165A1
ROUND FOR REROUND MODE IN A DECIMAL FLOATING POINT INSTRUCTION
Publication/Patent Number: US2018121165A1 Publication Date: 2018-05-03 Application Number: 15/852,180 Filing Date: 2017-12-22 Inventor: Yeh, Phil C   Smith, Sr. Ronald M   Schwarz, Eric M   Cowlishaw, Michael F   Assignee: International Business Machines Corporation   IPC: G06F7/483 Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
15 US2018113826A1
STORAGE APPARATUS ACCESSED BY USING MEMORY BUS
Publication/Patent Number: US2018113826A1 Publication Date: 2018-04-26 Application Number: 15/834,016 Filing Date: 2017-12-06 Inventor: Li, Yansong   Assignee: HUAWEI TECHNOLOGIES CO., LTD.   IPC: G06F13/42 Abstract: A storage apparatus accessed by using a memory bus is disclosed. The apparatus includes an interface controller, a storage module, a storage controller, a command register, a status register, and a buffer. In addition, the interface controller can be electrically connected to a memory module interface of a computer system. The interface controller receives an access command for accessing the storage module sent by a CPU. The interface controller writes the access command into the command register, and records a current access status or result by using the status register. The storage controller performs status setting on the status register according to the access command in the command register, and performs a corresponding read/write operation on the storage module.
16 US2018164910A1
WIDE TOUCHPAD
Publication/Patent Number: US2018164910A1 Publication Date: 2018-06-14 Application Number: 15/373,401 Filing Date: 2016-12-08 Inventor: Ent, Ali Kathryn   Assignee: Lenovo (Singapore) Pte. Ltd.   IPC: G06F3/0488 Abstract: An apparatus can include a processor; memory accessible by the processor; and a display housing, a keyboard housing and a hinge assembly that rotatably couples the display housing and the keyboard housing where the keyboard housing includes a hinge assembly end, a front end, a left side and a right side; a keyboard that includes a spacebar, an S key, an L key and an S-to-L key distance; and a touchpad disposed between the spacebar and the front end that extends a left side to right side distance greater than the S-to-L key distance.
17 US2018218143A1
ELECTRONIC APPARATUS, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM STORING LOCK MANAGING PROGRAM
Publication/Patent Number: US2018218143A1 Publication Date: 2018-08-02 Application Number: 15/877,222 Filing Date: 2018-01-22 Inventor: Arakawa, Hiroki   Assignee: Kyocera Document Solutions   IPC: G06F3/0488 Abstract: In an electronic apparatus, a display device displays an unlock screen that includes a mark pattern of one or plural marks. A touch panel (a) detects as one unlock operation a user operation performed at one time to a part or all of the one or plural marks and (b) is capable of detecting as a registered unlock operation pattern the unlock operations performed a preset number of times. A lock managing unit (a) displays the unlock screen on the display device in a lock status that restricts user operations, (b) determines user operations detected plural times by the touch panel, (c) determines whether the determined user operations of plural times agree with the registered unlock operation pattern or not, and (d) cancels the lock status if the determined user operations of plural times agree with the registered unlock operation pattern.
18 US2018181416A1
INFORMATION PROCESSING APPARATUS, IC CHIP, INFORMATION PROCESSING METHOD, PROGRAM, AND INFORMATION PROCESSING SYSTEM
Publication/Patent Number: US2018181416A1 Publication Date: 2018-06-28 Application Number: 15/901,002 Filing Date: 2018-02-21 Inventor: Mitsuyu, Gaku   Assignee: SONY CORPORATION   IPC: G06F9/4401 Abstract: There is provided an information processing apparatus, including a multi-platform capable of managing a plurality of applications, and an operating system which operates on the multi-platform, and is capable of being activated by a command of the multi-platform.
19 US2018232289A1
DATA ENCODING USING SPARE CHANNELS
Publication/Patent Number: US2018232289A1 Publication Date: 2018-08-16 Application Number: 15/954,149 Filing Date: 2018-04-16 Inventor: Hollis, Timothy Mowry   Assignee: Micron Technology, Inc.   IPC: G06F13/28 Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.
20 US2018225045A1
HIGH PERFORMANCE OPTICAL STORAGE SYSTEM FOR PROTECTION AGAINST CONCURRENT DATA LOSS
Publication/Patent Number: US2018225045A1 Publication Date: 2018-08-09 Application Number: 15/940,471 Filing Date: 2018-03-29 Inventor: Rees, Robert M.   Hineman, Wayne C.   Hetzler, Steven R.   Blaum, Mario   Assignee: International Business Machines Corporation   IPC: G06F12/127 Abstract: A controller including an object aggregator process that combines multiple data objects into a data segment, and transfers the data segment with reduced location metadata to storage media of at least one of multiple storage units. An erasure coder process generates code to encode the data segment into an erasure code that protects against concurrent data loss in the multiple storage units based on data reconstruction using a first responder, a second responder and a last responder.