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1 | US10090303B2 |
Fabrication of vertical field effect transistors with uniform structural profiles
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Publication/Patent Number: US10090303B2 | Publication Date: 2018-10-02 | Application Number: 15/789,217 | Filing Date: 2017-10-20 | Inventor： Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: H01L27/088 | Abstract: Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods for vertical FET devices implement a process flow to fabricate dummy fins within isolation regions to enable the formation of vertical FET devices with uniform structural profiles within device regions. Sacrificial semiconductor fins are formed in the isolation regions concurrently with semiconductor fins in the device regions, to minimize/eliminate micro-loading effects from an etch process used for fin patterning and, thereby, form uniform profile semiconductor fins. The sacrificial semiconductor fins within the isolation regions also serve to minimize/eliminate non-uniform topography and micro-loading effects when planarizing and recessing conductive gate layers and, thereby. form conductive gate structures for vertical FET devices with uniform gate lengths in the device regions. The sacrificial semiconductor fins are subsequently removed and replaced with insulating material to form the dummy fins. | |||
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2 | US10083839B2 |
Sidewall image transfer (SIT) methods with localized oxidation enhancement of sacrificial mandrel sidewall by ion beam exposure
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Publication/Patent Number: US10083839B2 | Publication Date: 2018-09-25 | Application Number: 15/647,689 | Filing Date: 2017-07-12 | Inventor： Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: H01L21/308 | Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins. | |||
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3 | US10014222B2 |
Fabrication of a vertical fin field effect transistor with reduced dimensional variations
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Publication/Patent Number: US10014222B2 | Publication Date: 2018-07-03 | Application Number: 15/627,927 | Filing Date: 2017-06-20 | Inventor： Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: H01L27/108 | Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins. | |||
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4 | US9859302B1 |
Fin-type field-effect transistor
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Publication/Patent Number: US9859302B1 | Publication Date: 2018-01-02 | Application Number: 15/196,353 | Filing Date: 2016-06-29 | Inventor： Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: H01L49/02 | Abstract: This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins. | |||
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5 | US9882005B2 |
Fully depleted silicon-on-insulator device formation
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Publication/Patent Number: US9882005B2 | Publication Date: 2018-01-30 | Application Number: 14/745,628 | Filing Date: 2015-06-22 | Inventor： Ozcan, Ahmet S Cheng, Kangguo Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: H01L21/3213 | Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device. | |||
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6 | US9859494B1 |
Nanoparticle with plural functionalities, and method of forming the nanoparticle
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Publication/Patent Number: US9859494B1 | Publication Date: 2018-01-02 | Application Number: 15/197,207 | Filing Date: 2016-06-29 | Inventor： Liu, Fei Cheng, Kangguo Cao, Qing Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: A61K9/14 | Abstract: A nanoparticle includes a cuboid base including a semiconductor material, and a plurality of surfaces formed on the base and including a plurality of functionalities, respectively. | |||
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7 | US9871118B2 |
Semiconductor structure with an L-shaped bottom plate
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Publication/Patent Number: US9871118B2 | Publication Date: 2018-01-16 | Application Number: 15/181,447 | Filing Date: 2016-06-14 | Inventor： Haensch, Wilfried E Cheng, Kangguo Cheng, Kangguo Sadana, Devendra K | Assignee: International Business Machines Corporation | IPC: H01L29/78 | Abstract: A semiconductor structure having an electrical contact that is connected to source/drain structures of two different transistors. The semiconductor structure has a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate. | |||
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8 | US9870989B2 |
Electrical fuse and/or resistor structures
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Publication/Patent Number: US9870989B2 | Publication Date: 2018-01-16 | Application Number: 15/466,380 | Filing Date: 2017-03-22 | Inventor： Basker, Veeraraghavan S Cheng, Kangguo Cheng, Kangguo Ponoth, Shom | Assignee: International Business Machines Corporation | IPC: H01L21/8234 | Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. | |||
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9 | US9954109B2 |
Vertical transistor including controlled gate length and a self-aligned junction
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Publication/Patent Number: US9954109B2 | Publication Date: 2018-04-24 | Application Number: 15/147,342 | Filing Date: 2016-05-05 | Inventor： Divakaruni, Ramachandra Cheng, Kangguo | Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION | IPC: H01L29/51 | Abstract: A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources. | |||
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10 | US10068898B2 |
On-chip MIM capacitor
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Publication/Patent Number: US10068898B2 | Publication Date: 2018-09-04 | Application Number: 15/416,349 | Filing Date: 2017-01-26 | Inventor： Cheng, Kangguo Xu, Peng | Assignee: International Business Machines Corporation | IPC: H01L27/108 | Abstract: A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region. | |||
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11 | US9923083B1 |
Embedded endpoint fin reveal
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Publication/Patent Number: US9923083B1 | Publication Date: 2018-03-20 | Application Number: 15/261,055 | Filing Date: 2016-09-09 | Inventor： Xu, Peng Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: H01L21/308 | Abstract: A method for fabricating a semiconductor structure includes forming a cut mask over a set of fin hard masks formed on a substrate. At least one gap defined at least in part by the cut mask is formed, and a first dielectric layer is formed within the at least one gap. A plurality of fins is formed, and the first dielectric layer is recessed to form an isolation region. A liner is deposited along exposed surfaces of the recessed first dielectric layer and the plurality of fins. A second dielectric layer is formed within a region defined by the liner and the plurality of fins. At least a portion of the second dielectric layer is removed to reveal the plurality of fins, wherein the portion of the second dielectric layer that is removed is based on the liner serving as an endpoint layer. | |||
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12 | US10002925B2 |
Strained semiconductor device
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Publication/Patent Number: US10002925B2 | Publication Date: 2018-06-19 | Application Number: 15/647,921 | Filing Date: 2017-07-12 | Inventor： Xu, Peng Cheng, Kangguo | Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION | IPC: H01L21/8238 | Abstract: A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width and a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin is arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width. A gate stack is arranged over a channel region of the first fin and a channel region of the second fin. | |||
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13 | US9997606B2 |
Fully depleted SOI device for reducing parasitic back gate capacitance
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Publication/Patent Number: US9997606B2 | Publication Date: 2018-06-12 | Application Number: 15/282,349 | Filing Date: 2016-09-30 | Inventor： Divakaruni, Ramachandra Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: H01L21/306 | Abstract: A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator, forming a dummy gate, and forming a source/drain next to the dummy gate, the source/drain defining a raised source/drain region. The method further includes depositing a dielectric material over the raised source/drain regions, removing the dummy gate to define a recess, implanting a species within a first layer of the bilayer buried insulator, and depositing a gate dielectric and a conducting material within the recess. The method further includes removing the substrate, etching the implanted portion of the first layer of the bilayer buried insulator to expose a surface of a second layer of the bilayer buried insulator, and forming a back gate over the exposed second layer, the back gate self-aligned to the ETSOI channel. | |||
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14 | US10043874B2 |
Uniform vertical field effect transistor spacers
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Publication/Patent Number: US10043874B2 | Publication Date: 2018-08-07 | Application Number: 15/817,325 | Filing Date: 2017-11-20 | Inventor： Li, Juntao Cheng, Kangguo | Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION | IPC: H01L29/78 | Abstract: Aspects of the disclosure include a semiconductor structure that includes a vertical fin structure having a top portion, a bottom portion, vertical side walls, a source area in contact with the vertical fin structure, a drain area in contact with the vertical fin structure, a plurality of spacers comprising a first oxide layer in contact with the source area, and a second oxide layer in contact with the drain area. The first oxide layer can have a thickness that is equal to a thickness of the second oxide layer. | |||
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15 | US10103063B2 |
Forming a hybrid channel nanosheet semiconductor structure
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Publication/Patent Number: US10103063B2 | Publication Date: 2018-10-16 | Application Number: 15/690,601 | Filing Date: 2017-08-30 | Inventor： Cheng, Kangguo Xu, Peng | Assignee: International Business Machines Corporation | IPC: H01L21/8238 | Abstract: A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having second inner spacer comprised of a second material. The first material is different than the second material. The first nanosheet FET structure is formed by creating a first inner spacer formation within a first silicon germanium (SiGe) channel, wherein the first SiGe channel is comprised in a first channel region of a first FET region. The second nanosheet FET structure is formed by creating a second inner spacer formation within a second SiGe channel, wherein the second SiGe channel is comprised in a second channel region of a second FET region. | |||
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16 | US9893169B1 |
Fabrication of a vertical fin field effect transistor having a consistent channel width
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Publication/Patent Number: US9893169B1 | Publication Date: 2018-02-13 | Application Number: 15/492,343 | Filing Date: 2017-04-20 | Inventor： Li, Juntao Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: H01L21/311 | Abstract: A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between. | |||
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17 | US9929256B2 |
Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch
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Publication/Patent Number: US9929256B2 | Publication Date: 2018-03-27 | Application Number: 15/474,551 | Filing Date: 2017-03-30 | Inventor： Cheng, Kangguo Xu, Peng | Assignee: International Business Machines Corporation | IPC: H01L21/8234 | Abstract: A method of forming an arrangement of active and inactive fins on a substrate, including forming at least three vertical fins on the substrate, forming a protective liner on at least three of the at least three vertical fins, removing at least a portion of the protective liner on the one of the at least three of the at least three of vertical fins, and converting the one of the at least three of the at least three vertical fins to an inactive vertical fin. | |||
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18 | US9917199B2 |
Method for reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions
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Publication/Patent Number: US9917199B2 | Publication Date: 2018-03-13 | Application Number: 15/439,078 | Filing Date: 2017-02-22 | Inventor： Divakaruni, Ramachandra Cheng, Kangguo | Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION | IPC: H01L29/66 | Abstract: A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side. | |||
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19 | US10056255B2 |
Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
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Publication/Patent Number: US10056255B2 | Publication Date: 2018-08-21 | Application Number: 15/464,817 | Filing Date: 2017-03-21 | Inventor： Li, Juntao Cheng, Kangguo | Assignee: International Business Machines Corporation | IPC: H01L21/30 | Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device. | |||
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20 | US9947740B1 |
On-chip MIM capacitor
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Publication/Patent Number: US9947740B1 | Publication Date: 2018-04-17 | Application Number: 15/498,714 | Filing Date: 2017-04-27 | Inventor： Xu, Peng Cheng, Kangguo | Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION | IPC: H01L21/8238 | Abstract: A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region. |
3.Current Quota