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1
US09859302B1
Publication/Patent Number: US09859302B1
Publication date: 2018-01-02
Application number: 15/196,353
Filing date: 2016-06-29
Inventor: Cheng, Kangguo  
Abstract: This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins. This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor ...more ...less
2
US10014222B2
Publication/Patent Number: US10014222B2
Publication date: 2018-07-03
Application number: 15/627,927
Filing date: 2017-06-20
Inventor: Cheng, Kangguo  
Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins. A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of ...more ...less
3
US10083839B2
Publication/Patent Number: US10083839B2
Publication date: 2018-09-25
Application number: 15/647,689
Filing date: 2017-07-12
Inventor: Cheng, Kangguo  
Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins. A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to ...more ...less
4
US10090303B2
Publication/Patent Number: US10090303B2
Publication date: 2018-10-02
Application number: 15/789,217
Filing date: 2017-10-20
Inventor: Cheng, Kangguo  
Abstract: Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods for vertical FET devices implement a process flow to fabricate dummy fins within isolation regions to enable the formation of vertical FET devices with uniform structural profiles within device regions. Sacrificial semiconductor fins are formed in the isolation regions concurrently with semiconductor fins in the device regions, to minimize/eliminate micro-loading effects from an etch process used for fin patterning and, thereby, form uniform profile semiconductor fins. The sacrificial semiconductor fins within the isolation regions also serve to minimize/eliminate non-uniform topography and micro-loading effects when planarizing and recessing conductive gate layers and, thereby. form conductive gate structures for vertical FET devices with uniform gate lengths in the device regions. The sacrificial semiconductor fins are subsequently removed and replaced with insulating material to form the dummy fins. Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods for vertical FET devices implement a process flow to fabricate dummy fins within isolation regions to enable the ...more ...less
5
US09882005B2
Publication/Patent Number: US09882005B2
Publication date: 2018-01-30
Application number: 14/745,628
Filing date: 2015-06-22
Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device. A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface ...more ...less
6
US9893181B1
Publication/Patent Number: US9893181B1
Publication date: 2018-02-13
Application number: 15/586,370
Filing date: 2017-05-04
Abstract: A method of fabricating a vertical field effect transistor includes forming a base layer on a doped layer that is formed on a substrate, and forming fin hard masks above the base layer. Spacers are formed adjacent to each side of each of the fin hard masks above the base layer. A width dimension of each of the spacers is the same. Gaps between the spacers are filled with oxide prior to removing the spacers. The spacers are removed to leave gaps of the same width on each side of each of the fin hard masks. An etch in the gaps forms a plurality of fins below the fin hard masks. A height dimension of each of the plurality of fins is the same and a space between two of the plurality of fins is different than a second space between two others of the plurality of fins. A method of fabricating a vertical field effect transistor includes forming a base layer on a doped layer that is formed on a substrate, and forming fin hard masks above the base layer. Spacers are formed adjacent to each side of each of the fin hard masks above the base layer ...more ...less
7
US10096698B2
Publication/Patent Number: US10096698B2
Publication date: 2018-10-09
Application number: 15/928,563
Filing date: 2018-03-22
Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device. Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces ...more ...less
8
US10068898B2
Publication/Patent Number: US10068898B2
Publication date: 2018-09-04
Application number: 15/416,349
Filing date: 2017-01-26
Abstract: A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region. A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate ...more ...less
9
US10068980B1
Publication/Patent Number: US10068980B1
Publication date: 2018-09-04
Application number: 15/498,054
Filing date: 2017-04-26
Abstract: A method of forming a gate structure with a modified gate geometry, including, forming two gate spacers and a dummy gate fill on a channel, wherein the dummy gate fill is between the two gate spacers, forming a stressed layer on the two gate spacers, wherein the stressed layer is on the surfaces of the gate spacers opposite the dummy gate fill, and wherein the stressed layer applies a tensile stress to the two gate spacers, and removing a portion of the dummy gate fill, wherein the tensile stress applied to the two gate spacers is no longer balanced by the dummy gate fill, such that each of the two gate spacers becomes inclined at an obtuse angle relative to a top surface of the remaining dummy gate fill. A method of forming a gate structure with a modified gate geometry, including, forming two gate spacers and a dummy gate fill on a channel, wherein the dummy gate fill is between the two gate spacers, forming a stressed layer on the two gate spacers, wherein the stressed layer ...more ...less
10
US10141320B1
Publication/Patent Number: US10141320B1
Publication date: 2018-11-27
Application number: 15/585,826
Filing date: 2017-05-03
Abstract: A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses. A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper ...more ...less
11
US09870948B2
Publication/Patent Number: US09870948B2
Publication date: 2018-01-16
Application number: 15/177,917
Filing date: 2016-06-09
Abstract: A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active device region and an isolation region. The composite fin structures may include a semiconductor portion over the active device region and a dielectric portion over the isolation region. A gate structure can be formed on the channel region of the fin structures that are present on the active regions of the substrate, and the gate structure is also formed on the dielectric fin structures on the isolation regions of the substrate. Epitaxial source and drain regions are formed on source and drain portions of the fin structures present on the active region, wherein the dielectric fin structures support the gate structure over the isolation regions. A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active device region and an isolation region. The composite fin structures may include a semiconductor portion over the ...more ...less
12
US09881839B1
Publication/Patent Number: US09881839B1
Publication date: 2018-01-30
Application number: 15/465,989
Filing date: 2017-03-22
Abstract: A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having second inner spacer comprised of a second material. The first material is different than the second material. A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having second inner spacer comprised of a second ...more ...less
13
US9923083B1
Publication/Patent Number: US9923083B1
Publication date: 2018-03-20
Application number: 15/261,055
Filing date: 2016-09-09
Abstract: A method for fabricating a semiconductor structure includes forming a cut mask over a set of fin hard masks formed on a substrate. At least one gap defined at least in part by the cut mask is formed, and a first dielectric layer is formed within the at least one gap. A plurality of fins is formed, and the first dielectric layer is recessed to form an isolation region. A liner is deposited along exposed surfaces of the recessed first dielectric layer and the plurality of fins. A second dielectric layer is formed within a region defined by the liner and the plurality of fins. At least a portion of the second dielectric layer is removed to reveal the plurality of fins, wherein the portion of the second dielectric layer that is removed is based on the liner serving as an endpoint layer. A method for fabricating a semiconductor structure includes forming a cut mask over a set of fin hard masks formed on a substrate. At least one gap defined at least in part by the cut mask is formed, and a first dielectric layer is formed within the at least one gap. A plurality ...more ...less
14
US9929046B2
Publication/Patent Number: US9929046B2
Publication date: 2018-03-27
Application number: 15/216,154
Filing date: 2016-07-21
Abstract: A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap. A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An ...more ...less