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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US8282970B2
Theaflavin compositions, related processes and methods of use
Publication/Patent Number: US8282970B2 Publication Date: 2012-10-09 Application Number: 12/574,862 Filing Date: 2009-10-07 Inventor: Shi, Xiaowei   Ren, Xueyin   Liu, Jianhong   Cao, Houjian   Ren, Wenhao   Cao, Yizhou   Assignee: Jiahgsu Dehe Bio-Tech Co., Ltd   IPC: A61K36/82 Abstract: A process for producing purified theaflavin extract is provided which comprises combining an organic solvent with tea leaves, extracting polyphenols from the tea leaves to produce an organic stock substrate solution; producing a second batch of tea leaves; grinding the second batch of tea leaves to produce stock fermentation enzyme; combining the stock substrate solution with the stock fermentation enzyme to produce a fermentation mixture; fermentation of the mixture to produce theaflavins; and, separating the theaflavins from the fermentation mixture to produce purified theaflavin extract. Oral dosage forms are provided which comprise an effective amount of the purified theaflavin extract. Methods of treatment of human physiological disorders are provided which comprise administering an oral dosage form.
2
US8282971B2
Degradable chewing gum
Publication/Patent Number: US8282971B2 Publication Date: 2012-10-09 Application Number: 11/923,229 Filing Date: 2007-10-24 Inventor: Soper, Paul D.   Miladinov, Vesselin Danailov   Amarista, Jose A.   Smith, Ian   Elleman, Carole   Taylor, Mark   Slater, Nigel Kenneth Harry   Eccleston, Mark Edward   Assignee: Kraft Foods Global Brands LLC   IPC: A23G4/08 Abstract: The present invention provides gum base compositions and chewing gum compositions having non stick or reduced-stick properties and/or increased degradability. Methods of preparing the gum base and chewing gum compositions, as well as methods of use, are provided.
3
US8282973B2
Container-packed milk coffee beverage
Publication/Patent Number: US8282973B2 Publication Date: 2012-10-09 Application Number: 11/997,212 Filing Date: 2006-07-28 Inventor: Shioya, Yasushi   Hayakawa, Yoshinobu   Kusaura, Tatsuya   Yamamoto, Shinji   Ogura, Yoshikazu   Assignee: Kao Corporation   IPC: B65D85/76 Abstract: Provision of a packaged milk coffee beverage having excellent hypertensive effects. A packaged milk coffee beverage satisfying the following conditions (A) to (C): (A) from 0.01 to 1 wt % of chlorogenic acids, (B) less than 0.1 wt % of hydroxyhydroquinone based on a content of the chlorogenic acids, and (C) a pH of from 5.0 to 6.4.
4
US8282977B2
Compositions containing non-polar compounds
Publication/Patent Number: US8282977B2 Publication Date: 2012-10-09 Application Number: 12/383,244 Filing Date: 2009-03-20 Inventor: Bromley, Philip J.   Assignee: Virun, Inc.   IPC: A23L2/385 Abstract: Provided herein are compositions and methods for preparing foods and beverages that contain additives, such as nutraceuticals, pharmaceuticals, and supplements, such as essential fatty acids, including omega-3 fatty acids, omega-6 fatty acids, conjugated fatty acids, and other fatty acids; phytochemicals, including phytosterols; other oils; and coenzymes, including Coenzyme Q10, and other oil-based additives.
5
US8284591B2
Semiconductor memory device and test method therefor
Publication/Patent Number: US8284591B2 Publication Date: 2012-10-09 Application Number: 12/696,608 Filing Date: 2010-01-29 Inventor: Asayama, Shinobu   Assignee: Renesas Electronics Corporation   IPC: G11C11/00 Abstract: Provided is a semiconductor memory device including: first and second SRAM cells; a first bit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell.
6
US8284597B2
Diode memory
Publication/Patent Number: US8284597B2 Publication Date: 2012-10-09 Application Number: 12/904,792 Filing Date: 2010-10-14 Inventor: Chang, Kuo-pin   Lue, Hang-ting   Assignee: Macronix International Co., Ltd.   IPC: G11C11/36 Abstract: A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.
7
US8284600B1
5-transistor non-volatile memory cell
Publication/Patent Number: US8284600B1 Publication Date: 2012-10-09 Application Number: 12/702,061 Filing Date: 2010-02-08 Inventor: Poplevine, Pavel   Ho, Ernes   Khan, Umer   Lin, Hengyang James   Assignee: National Semiconductor Corporation   IPC: G11C11/34 Abstract: A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.
8
US8284609B2
Compensation of non-volatile memory chip non-idealities by program pulse adjustment
Publication/Patent Number: US8284609B2 Publication Date: 2012-10-09 Application Number: 13/151,938 Filing Date: 2011-06-02 Inventor: Mokhlesi, Nima   Zhao, Dengtao   Chin, Henry   Samaddar, Tapan   Assignee: SanDisk Technologies Inc.   IPC: G11C11/34 Abstract: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.
9
US8284615B2
Refresh control circuit and method for semiconductor memory device
Publication/Patent Number: US8284615B2 Publication Date: 2012-10-09 Application Number: 12/979,678 Filing Date: 2010-12-28 Inventor: Shim, Young-bo   Assignee: Hynix Semiconductor Inc.   IPC: G11C11/34 Abstract: A refresh control circuit for a semiconductor memory device includes a refresh controller configured to control the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, and a mode determination signal having refresh mode information, a refresh counter configured to output a row address for a refresh operation by counting the refresh signal in response to an active signal enabled in an active mode, and a row address decoder configured to decode the row address to generate a row address selection signal for sequentially accessing word lines within a cell array.
10
US8284617B2
Circuits, devices, systems, and methods of operation for capturing data signals
Publication/Patent Number: US8284617B2 Publication Date: 2012-10-09 Application Number: 13/438,756 Filing Date: 2012-04-03 Inventor: Johnson, James Brian   Assignee: Micron Technology, Inc.   IPC: G11C7/00 Abstract: Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received.
11
US8284619B2
Semiconductor integrated circuit and system
Publication/Patent Number: US8284619B2 Publication Date: 2012-10-09 Application Number: 12/134,843 Filing Date: 2008-06-06 Inventor: Nakakubo, Atsushi   Assignee: Fujitsu Semiconductor Limited   IPC: G11C5/14 Abstract: An internal circuit has a plurality of circuit blocks operating by receiving an internal power supply voltage. An internal voltage control circuit generates a plurality of regulator control signals according to a combination of operating circuit blocks. A plurality of regulators operate in response to activation of the regulator control signals respectively to generate the internal power supply voltage by using an external power supply voltage. For example, as the number of the operating circuit blocks increases, the number of the operating regulators increases. By thus generating the regulator control signals according to the actual operation of the internal circuit to control the operations of the regulators, it is possible to reduce variation in the internal power supply voltage to a minimum. As a result, an operating margin of a semiconductor integrated circuit can be improved and a yield of the semiconductor integrated circuit can be improved.
12
US8284620B2
Memory controller-adaptive 1T/2T timing control
Publication/Patent Number: US8284620B2 Publication Date: 2012-10-09 Application Number: 12/502,628 Filing Date: 2009-07-14 Inventor: Reed, David G.   Assignee: NVIDIA Corporation   IPC: G11C7/00 Abstract: Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing.
13
US8283444B2
Non-viral delivery of compounds to mitochondria
Publication/Patent Number: US8283444B2 Publication Date: 2012-10-09 Application Number: 10/972,222 Filing Date: 2004-10-22 Inventor: Payne, R. Mark   Assignee: Wake Forest University   IPC: C07K1/00 Abstract: A conjugate comprises: (a) a mitochondrial membrane-permeant peptide; (b) an active agent or compound of interest such as a detectable group or mitochondrial protein or peptide; and (c) a mitochondrial targeting sequence linking said mitochondrial membrane-permeant peptide and said active mitochondrial protein or peptide. The targeting sequence is one which is cleaved within the mitochondrial matrix, and not cleaved within the cellular cytoplasm, of a target cell into which said compound is delivered. Methods of use of such compounds are also described.
14
US8283447B2
Immunosuppressive polypeptides and nucleic acids
Publication/Patent Number: US8283447B2 Publication Date: 2012-10-09 Application Number: 13/011,463 Filing Date: 2011-01-21 Inventor: Karrer, Erik E.   Paidhungat, Madan M.   Bass, Steven H.   Neighbors, Margaret   Punnonen, Juha   Chapin, Steven J.   Assignee: Perseid Therapeutics LLC   IPC: C07K14/705 Abstract: The invention provides immunosuppressive polypeptides and nucleic acids encoding such polypeptides. In one aspect, the invention provides mutant CTLA-4 polypeptides and nucleic acids encoding mutant CTLA-4 polypeptides. Compositions and methods for utilizing such polypeptides and nucleic acids are also provided.
15
US8283451B2
Kit for prediction of pre-eclampsia
Publication/Patent Number: US8283451B2 Publication Date: 2012-10-09 Application Number: 13/213,802 Filing Date: 2011-08-19 Inventor: Poston, Lucilla   Seed, Paul Townsend   Hunt, Beverley Jane   Chappell, Lucy Charlotte   Assignee: Perkinelmer Las, Inc.   IPC: C07K16/00 Abstract: The present invention relates to a method of predicting pre-eclampsia (PE). The present invention also relates to a diagnostic kit for performing a method of predicting PE. In particular, the method determining the level of two or more markers selected from placenta growth factor (PlGF), plasminogen activator inhibitor-1 (PAI-1), plasminogen activator inhibitor-2 (PAI-2) and leptin.
16
US8283454B2
Processes for the preparation of SGLT2 inhibitors
Publication/Patent Number: US8283454B2 Publication Date: 2012-10-09 Application Number: 12/545,400 Filing Date: 2009-08-21 Inventor: Liou, Jason   Wu, Yuelin   Li, Shengbin   Xu, Ge   Assignee: Theracos, Inc.   IPC: C07H1/00 Abstract: Provided are processes for the preparation of complexes that are useful in purifying compounds having an inhibitory effect on sodium-dependent glucose cotransporter SGLT. The processes can reduce the number of steps needed to obtain the target compounds and the complexes formed in the processes are typically provided in a crystalline form.
17
US8284547B2
Display apparatus and method for assembling the same
Publication/Patent Number: US8284547B2 Publication Date: 2012-10-09 Application Number: 12/156,231 Filing Date: 2008-05-29 Inventor: Kim, Dong-gyu   Assignee: Samsung Electronics Co., Ltd.   IPC: G06F1/16 Abstract: In a display apparatus and a method for assembling the display apparatus, the display apparatus includes for an embodiment a backlight assembly, a lower receiving member, a display panel and an upper receiving member. The backlight assembly provides light. The lower receiving member receives the backlight assembly. The display panel is disposed over the backlight assembly. An end portion of the upper receiving member is disposed on a non-display area of the first substrate and protrudes between an end portion of the front case and the first substrate. The upper receiving member is combined with the lower receiving member and fixes the display panel. Thus, the display panel may be safely fixed (secured).
18
US8284548B2
Frame casing and display device
Publication/Patent Number: US8284548B2 Publication Date: 2012-10-09 Application Number: 12/450,512 Filing Date: 2008-03-25 Inventor: Takechi, Yoshihiro   Assignee: NEC Display Solutions, Ltd.   IPC: G06F1/16 Abstract: A frame casing according to the present invention is provided on side surfaces of a display section, and includes: a plurality of divided frames which are L-shaped and disposed along the side surfaces of the display section with adjacent ends thereof along a circumferential direction overlapping one another; and a attaching section which is formed in a middle of a circumferential direction of each of the plurality of divided frames and which attaches the plurality of divided frames to the side surfaces of the display section, total length of the divided frames along the circumferential direction being greater than total length of the side surfaces of the display section along the circumferential direction.
19
US8284555B2
Heat-dissipated fastener and elastic frame thereof
Publication/Patent Number: US8284555B2 Publication Date: 2012-10-09 Application Number: 12/615,934 Filing Date: 2009-11-10 Inventor: Wang, Cheng-yu   Assignee: ASUSTeK Computer Inc.   IPC: H05K7/20 Abstract: A heat-dissipated fastener including a heat-dissipated plate, an elastic frame and a heat sink module is provided. The elastic frame includes a sheet element, multiple connecting ribs and multiple attaching portions. Two elastic arms extend from two corresponding sides of the sheet element, respectively. The attaching portions are located below the sheet element and attached to the heat-dissipated plate. The connecting ribs are connected to the attaching portion and the sheet element, and an accommodating space is formed by the connecting ribs, the sheet element and the heat-dissipated plate to accommodate the heat sink module. When the heat-dissipated plate is attached to the heat source and the elastic arms are bent and fixed to the circuit board of the heat source, the connecting ribs exert force on the heat-dissipated plate vertically, respectively.
20
US8284556B2
Electronic substrate device
Publication/Patent Number: US8284556B2 Publication Date: 2012-10-09 Application Number: 13/096,020 Filing Date: 2011-04-28 Inventor: Nishiuma, Yoshitake   Hashimoto, Koji   Assignee: Mitsubishi Electric Corporation   IPC: H05K7/20 Abstract: This invention is to provide an electronic substrate device which is capable of reliably and stably transferring heat generated by a heat generating component to a base member serving as a heat dissipater without intermediation of an electronic substrate. An electronic substrate device according to the present invention, in which a base member (10A) includes a central protruding portion (15A) which is accommodated in a penetrating portion (32A) while facing a die pad (42A) through an intermediation of a first gap (G1), and first separated protruding portions (17a and 17b) which are provided around the central protruding portion (15A) and have a height dimension smaller than that of the central protruding portion (15A), the first separated protruding portions (17a and 17b) having a top surface which abuts a rear surface portion of the electronic substrate (30A) to form a second gap (G2), and in which a first heat transfer bond (16A) which is a heat conductive adhesive is applied to the first gap (G1) and the second gap (G2) communicating with the first gap (G1).
Total 500 pages