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1
US9287292B2
Publication/Patent Number: US9287292B2
Publication date: 2016-03-15
Application number: 27/783,308
Filing date: 2008-11-25
Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support ...more ...less
2
US9287400B2
Publication/Patent Number: US9287400B2
Publication date: 2016-03-15
Application number: 20/121,358
Filing date: 2012-08-16
Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in ...more ...less
3
US20150084064A1
Publication/Patent Number: US20150084064A1
Publication date: 2015-03-26
Application number: 14/381,562
Filing date: 2012-05-18
Abstract: The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1. The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate ...more ...less
4
WO2013171892A1
Publication/Patent Number: WO2013171892A1
Publication date: 2013-11-21
Application number: 2012062772
Filing date: 2012-05-18
Abstract: This semiconductor device has: a gate electrode (GE) formed on a substrate with a gate insulating film (GI) therebetween; and a semiconductor layer (EP1) for a source/drain formed on the substrate. The upper surface of the semiconductor layer (EP1) is at a position higher than the upper surface of the substrate directly beneath the gate electrode (GE). Also This semiconductor device has: a gate electrode (GE) formed on a substrate with a gate insulating film (GI) therebetween; and a semiconductor layer (EP1) for a source/drain formed on the substrate. The upper surface of the semiconductor layer (EP1) is at a position higher than ...more ...less
5
US20120309157A1
Publication/Patent Number: US20120309157A1
Publication date: 2012-12-06
Application number: 13/587,361
Filing date: 2012-08-16
Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable. An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in ...more ...less
6
US7834377B2
Publication/Patent Number: US7834377B2
Publication date: 2010-11-16
Application number: 73/335,107
Filing date: 2007-04-10
Inventor: Iwamatsu, Toshiaki  
Abstract: A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1
7
US7838349B2
Publication/Patent Number: US7838349B2
Publication date: 2010-11-23
Application number: 13/182,608
Filing date: 2008-06-02
Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure
8
US20090096036A1
Publication/Patent Number: US20090096036A1
Publication date: 2009-04-16
Application number: 12/248,250
Filing date: 2008-10-09
Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided. There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the ...more ...less
9
US20080179676A1
Publication/Patent Number: US20080179676A1
Publication date: 2008-07-31
Application number: 11/971,434
Filing date: 2008-01-09
Abstract: While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and the drain region of a load transistor, and the electrical coupling between the drain region of another driver transistor (which is also a source/drain region of another access transistor) and the drain region of another load transistor are established by wiring structures formed by using a SOI layer under an isolation oxide film which is partial trench isolation, respectively. While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain ...more ...less
10
US7224484B1
Publication/Patent Number: US7224484B1
Publication date: 2007-05-29
Application number: 09/680,543
Filing date: 2000-10-04
Abstract: When a sensor of a scanning array is identified as “bad” (defective), data from a neighboring “good” sensor is used to determine pixel data nominally associated with the bad sensor. During a calibration procedure, dark-offset and gain values are determined for each sensor to compensate for individual differences between the sensors of the array. These values are entered into a table in memory. During scanning of an actual image, the values are used to determine digital image pixel data from the signal data provided by the sensors. The calibration procedure also identifies bad sensors, e.g., sensors that remain on or off, irrespective of the illumination incident to them. Extreme offset and gain values are entered into the table locations associated with the respective sensor. When the extreme values are detected, the signal data for the respective sensor is discarded, and the pixel data associated with the most recently processed good sensor is used as the pixel data associated with the bad sensor. Thus, instead of being all white or all dark, pixels associated with a bad sensor match neighboring pixels. Generally, this result is far more acceptable perceptually. Thus, a scanner can have a useful life beyond the failure of one or more sensors of the scanning array. When a sensor of a scanning array is identified as “bad” (defective), data from a neighboring “good” sensor is used to determine pixel data nominally associated with the bad sensor. During a calibration procedure, dark-offset and gain values are ...more ...less
11
US20040115905A1
Publication/Patent Number: US20040115905A1
Publication date: 2004-06-17
Application number: 10/318,304
Filing date: 2002-12-13
Abstract: The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising: a first sacrificial oxidation stage for removing material constituting the working layer (6) over a certain surface thickness of each substrate (1), a stage of polishing (200) the face which has been subjected to the first sacrificial oxidation stage (100), and a second sacrificial oxidation stage for again removing material constituting the working layer (6) on the polished face (17). The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising: a first sacrificial ...more ...less
12
US20030042542A1
Publication/Patent Number: US20030042542A1
Publication date: 2003-03-06
Application number: 08/709,071
Filing date: 1996-09-06
Abstract: A semiconductor layer has one end placed on top of a first conductive layer and in contact with the first conductive layer, and the other end placed on top of a second conductive layer and in contact with the second conductive layer. At the central portion, the semiconductor layer faces a gate electrode layer with a gate insulating layer interposed therebetween. The semiconductor layer is formed so that its width W1 is smaller than its height H1. As a result, a thin film transistor and manufacturing method thereof can be obtained in which contact between a source/drain region of the thin film transistor and an upper or lower conductive layer can be made stably. A semiconductor layer has one end placed on top of a first conductive layer and in contact with the first conductive layer, and the other end placed on top of a second conductive layer and in contact with the second conductive layer. At the central portion, the semiconductor ...more ...less