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1
US10268576B2
Publication/Patent Number: US10268576B2
Publication date: 2019-04-23
Application number: 15/914,875
Filing date: 2018-03-07
Abstract: An object of the present invention is to provide a semiconductor device and a control method thereof that can suppress a circuit scale from being increased while maintaining a high interruption response performance. According to an embodiment, a semiconductor device includes a flash memory in which N interruption subroutine programs are stored, an interruption control circuit that detects occurrence of an interruption, counters that determine the respective occurrence probabilities of N interruption factors on the basis of the detection result of the interruption control circuit, an interruption buffer memory in which the M (M<N) interruption subroutine programs corresponding to the top M interruption factors determined to be high in the occurrence probability among the N interruption factors are stored, and a CPU that reads, in the case where an interruption of one of the M interruption factors has occurred, the interruption subroutine program corresponding to the interruption from the interruption buffer memory to execute the same. An object of the present invention is to provide a semiconductor device and a control method thereof that can suppress a circuit scale from being increased while maintaining a high interruption response performance. According to an embodiment, a semiconductor device includes a ...more ...less
2
US10269631B2
Publication/Patent Number: US10269631B2
Publication date: 2019-04-23
Application number: 15/679,310
Filing date: 2017-08-17
Abstract: As a barrier metal film, a titanium film is formed by a sputtering process, and a titanium nitride film is formed to cover the titanium film by a CVD process. Next, the back surface of a semiconductor substrate is cleaned by spraying a cleaning chemical liquid toward the back surface thereof, and a portion of the barrier metal film located in the outer peripheral portion is removed by causing the cleaning chemical liquid to wrap around toward the surface side of the outer peripheral portion from the back surface side. Next, a tungsten film is formed to cover the barrier metal film by a CVD process. As a barrier metal film, a titanium film is formed by a sputtering process, and a titanium nitride film is formed to cover the titanium film by a CVD process. Next, the back surface of a semiconductor substrate is cleaned by spraying a cleaning chemical liquid toward the back ...more ...less
3
US20190004966A1
Publication/Patent Number: US20190004966A1
Publication date: 2019-01-03
Application number: 15/981,540
Filing date: 2018-05-16
Inventor: Abematsu, Takashi  
Abstract: A semiconductor device includes associative memory, associated memory, a conversion register, a controller, and a synthetic data output unit. The associative memory searches whether input search data hits entry data stored in every row of a memory cell array or not, and outputs address information corresponding to hit entry data. The associated memory is accessibly provided according to address information in the associative memory and stores associated data corresponding to the entry data. The conversion register is capable of converting address information output from the associative memory into different address information. The controller accesses the associated memory based on address information in accordance with an output result from the conversion register and acquires associated data corresponding to the entry data. The synthetic data output unit that outputs synthetic data outside by synthesizing the address information output from the associative memory and associated data output from the associated memory. A semiconductor device includes associative memory, associated memory, a conversion register, a controller, and a synthetic data output unit. The associative memory searches whether input search data hits entry data stored in every row of a memory cell array or not, and outputs ...more ...less
4
US20190006978A1
Publication/Patent Number: US20190006978A1
Publication date: 2019-01-03
Application number: 15/979,005
Filing date: 2018-05-14
Abstract: A calculation apparatus 100 includes an encoder 101 configured to detect rising edges of PWM signals having at least three or more phases in each of the phases, and a register 103 configured to store, at a timing after the PWM signals having the respective phases rise and after AD conversion of a current value of a drive signal of a motor obtained by the PWM signals, a difference value between the AD-converted current value and a previous AD-converted current value for each phase. A calculation apparatus 100 includes an encoder 101 configured to detect rising edges of PWM signals having at least three or more phases in each of the phases, and a register 103 configured to store, at a timing after the PWM signals having the respective phases rise and after ...more ...less
5
US20190006268A1
Publication/Patent Number: US20190006268A1
Publication date: 2019-01-03
Application number: 15/985,957
Filing date: 2018-05-22
Abstract: A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions. A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a ...more ...less
6
US20190006364A1
Publication/Patent Number: US20190006364A1
Publication date: 2019-01-03
Application number: 15/985,280
Filing date: 2018-05-21
Abstract: According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions different from one another, a deep N-well formed in a part deeper than the shallow P-well and the shallow N-well, and a base material, and further includes a first transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, and a second transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, in which the shallow N-well is formed in such a way as to surround the peripheral edge of the region of the shallow P-well. According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions different from one another, a deep N-well formed in a part deeper than the shallow P-well and the shallow N-well, and a base ...more ...less
7
US20190043582A1
Publication/Patent Number: US20190043582A1
Publication date: 2019-02-07
Application number: 16/030,136
Filing date: 2018-07-09
Inventor: Yabuuchi, Makoto  
Abstract: A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each other in planar view, and the first and second word lines are formed using wirings of a first wiring layer. The first and second match lines are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first and second word lines are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first and second match lines are provided in parallel with each other between two second wirings to which the first reference potential is supplied. A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each ...more ...less
8
US20190074788A1
Publication/Patent Number: US20190074788A1
Publication date: 2019-03-07
Application number: 16/046,349
Filing date: 2018-07-26
Abstract: Provided are a motor angle detector for detecting a motor angle, a current detector for detecting a motor current value to drive a motor, a vehicle inclination angle detector for detecting a vehicle inclination angle, a motor control circuit for outputting a control signal to control the driving of the motor, and a storage apparatus. The storage apparatus stores data obtained by associating the motor current value, a setting value in the motor control circuit for outputting the control signal, the vehicle inclination angle, and the motor angle at a first time with each other, and the motor control circuit controls the driving of the motor on the basis of information of the motor current value and the vehicle inclination angle at a second time and the data at the first time. Provided are a motor angle detector for detecting a motor angle, a current detector for detecting a motor current value to drive a motor, a vehicle inclination angle detector for detecting a vehicle inclination angle, a motor control circuit for outputting a control signal to ...more ...less
9
US20190081057A1
Publication/Patent Number: US20190081057A1
Publication date: 2019-03-14
Application number: 16/036,324
Filing date: 2018-07-16
Inventor: Yamashita, Tomohiro  
Abstract: On the upper surface of a fin projecting from the upper surface of a semiconductor substrate, there are formed a control gate electrode through a gate insulating film and a memory gate electrode through a gate insulating film. A semiconductor region is formed in the fin beside the control gate electrode. On the semiconductor region, an insulating film, a first interlayer insulating film, and a second interlayer insulating film are formed. A plug reaching the semiconductor region is formed in the second interlayer insulating film, the first interlayer insulating film, and the insulating film. A cap film is formed between the control gate electrode and the interlayer insulating film, and the plug is positioned also right above the cap film. On the upper surface of a fin projecting from the upper surface of a semiconductor substrate, there are formed a control gate electrode through a gate insulating film and a memory gate electrode through a gate insulating film. A semiconductor region is formed in the fin beside ...more ...less
10
US10199481B2
Publication/Patent Number: US10199481B2
Publication date: 2019-02-05
Application number: