Country
Full text data for US and EP
Status
Type
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC
No.
Publication Number
Title
Publication/Patent Number Publication/Patent Number
Publication Date Publication Date
Application Number Application Number
Filing Date Filing Date
Inventor Inventor
Assignee Assignee
IPC IPC
1
US2020019202A1
Publication/Patent Number: US2020019202A1
Publication Date: 2020-01-16
Application Number: 16/202,753
Filing Date: 2018-11-28
Abstract: A current source circuit includes an initial bias generator and a diode-connected first metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain. The drain of the diode-connected MOS transistor is connected to the initial bias generator. The current source circuit also includes a second MOS transistor, a first resistor, and a current mirror. The second MOS transistor has a gate connected to the gate and drain of the diode-connected first MOS transistor. The first resistor is coupled between a source of the second MOS transistor and a ground node. The current mirror is coupled to a drain of the second MOS transistor and generates bias current for other components within the current source circuit. A current source circuit includes an initial bias generator and a diode-connected first metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain. The drain of the diode-connected MOS transistor is connected to the initial bias generator. The current source ...More ...Less
2
US2020019374A1
Publication/Patent Number: US2020019374A1
Publication Date: 2020-01-16
Application Number: 16/237,447
Filing Date: 2018-12-31
Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory. An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in ...More ...Less
3
US2020018782A1
Publication/Patent Number: US2020018782A1
Publication Date: 2020-01-16
Application Number: 16/363,779
Filing Date: 2019-03-25
Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node. Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first ...More ...Less
4
US2020021281A1
Publication/Patent Number: US2020021281A1
Publication Date: 2020-01-16
Application Number: 16/357,975
Filing Date: 2019-03-19
Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node. Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a ...More ...Less
5
US2020021285A1
Publication/Patent Number: US2020021285A1
Publication Date: 2020-01-16
Application Number: 16/227,636
Filing Date: 2018-12-20
Inventor: Chauhan, Rajat  
Abstract: A circuit includes a first transistor including first and second current terminals. The first current terminal couples to a supply voltage node. A second transistor includes a second control input and third and fourth current terminals. The third current terminal couples to the second current terminal at an output node and the fourth current terminal couples to a ground node. A third transistor includes a third control input and fifth and sixth current terminals. The fifth current terminal couples to the output node and the sixth current terminal couples to the ground node. A fourth transistor includes a fourth control input and seventh and eighth current terminals. The eighth current terminal couples to the ground node and the seventh current terminal couples to the third control input. An inverter having an input coupled to the second control input and an output coupled to the fourth control input. A circuit includes a first transistor including first and second current terminals. The first current terminal couples to a supply voltage node. A second transistor includes a second control input and third and fourth current terminals. The third current terminal couples to the ...More ...Less
6
US2020007376A1
Publication/Patent Number: US2020007376A1
Publication Date: 2020-01-02
Application Number: 16/559,667
Filing Date: 2019-09-04
Abstract: A method of operating a wireless communication system is disclosed. The method includes receiving first and second parallel data streams. The first data stream is converted to a first frequency-domain data stream by a discrete Fourier transform (DFT) having NDFT0 size, where NDFT0 is a positive integer. The second data stream is converted to a second frequency-domain data stream by a DFT having NDFT1 size, where NDFT1 is a positive integer. The first and second frequency-domain data streams are mapped to respective subcarriers. A method of operating a wireless communication system is disclosed. The method includes receiving first and second parallel data streams. The first data stream is converted to a first frequency-domain data stream by a discrete Fourier transform (DFT) having NDFT0 size, where ...More ...Less
7
US2020007189A1
Publication/Patent Number: US2020007189A1
Publication Date: 2020-01-02
Application Number: 16/021,175
Filing Date: 2018-06-28
Abstract: An inductively coupled multi-channel digital isolator where the transmitter and receiver inductive loops of a given channel are coplanar. In the case where two adjacent channels flow data in opposite directions, the receiver inductive loops of a given channel include a large, generally conventional loop portion and a small loop portion that is located inside the transmitter inductive loops of the adjacent channels. The sizes of the small loop portion and the conventional loop portion are generally in the ratio of the magnetic flux in the conventional loop portion to the magnetic flux in the transmitter inductive loop. This size relationship results in the voltage of the small loop portion being very close but opposite in sign to the voltage in the conventional loop portion. As a result, there is minimal crosstalk from the transmitter inductive loop of one channel to the receiver inductive loop of the adjacent channel. An inductively coupled multi-channel digital isolator where the transmitter and receiver inductive loops of a given channel are coplanar. In the case where two adjacent channels flow data in opposite directions, the receiver inductive loops of a given channel include a large ...More ...Less
8
US2020007148A1
Publication/Patent Number: US2020007148A1
Publication Date: 2020-01-02
Application Number: 16/564,059
Filing Date: 2019-09-09
Abstract: In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator. In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches ...More ...Less
9
US2020012304A1
Publication/Patent Number: US2020012304A1
Publication Date: 2020-01-09
Application Number: 16/208,159
Filing Date: 2018-12-03
Abstract: An apparatus includes a power transistor to conduct a load current from a supply voltage node to an output node and a current sense circuit coupled to the power transistor. The current sense circuit generates a current sense current proportional to the load current. A temperature sense circuit is included to generate a temperature sense voltage proportional to the temperature of the power FET. A thermal limit circuit is coupled to the temperature sense circuit. A current limit circuit is coupled to the current sense circuit and to the thermal limit circuit. The current limit circuit generates a control signal on a current limit circuit output node. The control signal is responsive to the current sense current and to a first current from the thermal limit circuit. The current limit circuit output node is coupled to a control input of the power transistor. An apparatus includes a power transistor to conduct a load current from a supply voltage node to an output node and a current sense circuit coupled to the power transistor. The current sense circuit generates a current sense current proportional to the load current. A ...More ...Less
10
US2020013528A1
Publication/Patent Number: US2020013528A1
Publication Date: 2020-01-09
Application Number: 16/576,809
Filing Date: 2019-09-20
Abstract: Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a plurality of resistor unit cells arranged in an array, each resistor unit cell formed within the semiconductor substrate and including a top contact. A conductive layer located over the semiconductor substrate electrically connects to a subset of the top contacts. Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a plurality of resistor unit cells arranged in an array, each resistor unit cell formed within the ...More ...Less
11
US2020022229A1
Publication/Patent Number: US2020022229A1
Publication Date: 2020-01-16
Application Number: 16/200,314
Filing Date: 2018-11-26
Abstract: Methods and apparatus to reduce a coupling effect in a light emitting diode (LED) display are disclosed. An example LED display includes an array of LEDs, and a line controller to select a line of LEDs of the array of LEDs for illumination. The example LED display wall includes a column controller to control illumination of at least two of the LEDs of the line of LEDs. The column controller is to cause, when the first brightness value is less than a threshold, a first LED to be illuminated during a first time period and a second LED to be illuminated during a second time period. The second period is distinct from the first time period. The first LED is a different color than the second LED. Methods and apparatus to reduce a coupling effect in a light emitting diode (LED) display are disclosed. An example LED display includes an array of LEDs, and a line controller to select a line of LEDs of the array of LEDs for illumination. The example LED display wall includes ...More ...Less
12
US2020014347A1
Publication/Patent Number: US2020014347A1
Publication Date: 2020-01-09
Application Number: 16/185,591
Filing Date: 2018-11-09
Abstract: A servo-amplifier includes a first bipolar transistor, a second bipolar transistor, a cascode transistor, and a bias transistor. The second bipolar transistor includes an emitter terminal that is connected to an emitter terminal of the first bipolar transistor to form a differential amplifier. The cascode transistor includes a source terminal that is connected to a collector terminal of the first bipolar transistor. The bias transistor is coupled to the first bipolar transistor, the second bipolar transistor and the cascode transistor. The bias transistor is configured to generate a bias voltage to drive a gate terminal of the cascode transistor based on a voltage at a base terminal of the first bipolar transistor and a voltage at a base terminal of the second bipolar transistor. As a result, neither of the bipolar transistors enters a saturation region during transient or steady state operation. A servo-amplifier includes a first bipolar transistor, a second bipolar transistor, a cascode transistor, and a bias transistor. The second bipolar transistor includes an emitter terminal that is connected to an emitter terminal of the first bipolar transistor to form a ...More ...Less
13
US10530308B2
Publication/Patent Number: US10530308B2
Publication Date: 2020-01-07
Application Number: 15/934,467
Filing Date: 2018-03-23
Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate. An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation ...More ...Less
14
US10526198B2
Publication/Patent Number: US10526198B2
Publication Date: 2020-01-07
Application Number: 13/411,849
Filing Date: 2012-03-05
Abstract: A MEMS IR sensor, with a cavity in a substrate underlapping an overlying layer and a temperature sensing component disposed in the overlying layer over the cavity, may be formed by forming an IR-absorbing sealing layer on the overlying layer so as to cover access holes to the cavity. The sealing layer is may include a photosensitive material, and the sealing layer may be patterned using a photolithographic process to form an IR-absorbing seal. Alternately, the sealing layer may be patterned using a mask and etch process to form the IR-absorbing seal. A MEMS IR sensor, with a cavity in a substrate underlapping an overlying layer and a temperature sensing component disposed in the overlying layer over the cavity, may be formed by forming an IR-absorbing sealing layer on the overlying layer so as to cover access holes to the ...More ...Less
15
US10535731B2
Publication/Patent Number: US10535731B2
Publication Date: 2020-01-14
Application Number: 15/955,122
Filing Date: 2018-04-17
Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension. An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the ...More ...Less