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1
US10170384B2
Publication/Patent Number: US10170384B2
Publication date: 2019-01-01
Application number: 15/620,361
Filing date: 2017-06-12
Abstract: Methods and apparatus providing a graded package for a semiconductor are disclosed. An example apparatus includes a die; and a graded package encapsulating the die, the graded package including a material that is spatially varied from a first location of the graded package to a second location of the graded package. Methods and apparatus providing a graded package for a semiconductor are disclosed. An example apparatus includes a die; and a graded package encapsulating the die, the graded package including a material that is spatially varied from a first location of the graded package to a ...more ...less
2
US10228736B2
Publication/Patent Number: US10228736B2
Publication date: 2019-03-12
Application number: 15/395,156
Filing date: 2016-12-30
Abstract: The reset isolation mechanism describes an embedded safety island inside a system on a chip which reduces the overall system cost while achieving functional safety. The safety island ensures an orderly shutdown of all or part of the rest of the system on a chip without the possibility of a safety island hang due to incomplete transactions at the time of the reset. The reset isolation mechanism describes an embedded safety island inside a system on a chip which reduces the overall system cost while achieving functional safety. The safety island ensures an orderly shutdown of all or part of the rest of the system on a chip without the ...more ...less
3
US10234889B2
Publication/Patent Number: US10234889B2
Publication date: 2019-03-19
Application number: 14/950,960
Filing date: 2015-11-24
Abstract: A proportional to absolute temperature (PTAT) generator, for example, generates a PTAT current (IPTAT) and a VBE (voltage base-to-emitter) in a first regulation loop. A voltage-to-current converter is operable to generate a complementary to absolute temperature current (ICTAT). The IPTAT and ICTAT are summed to obtain a zero temperature coefficient current (IZTC). One ICTAT and one resistor are used to generate the IZTC signal. A proportional to absolute temperature (PTAT) generator, for example, generates a PTAT current (IPTAT) and a VBE (voltage base-to-emitter) in a first regulation loop. A voltage-to-current converter is operable to generate a complementary to absolute temperature current (ICTAT) ...more ...less
4
US20190087681A1
Publication/Patent Number: US20190087681A1
Publication date: 2019-03-21
Application number: 15/707,695
Filing date: 2017-09-18
Abstract: Systems and methods for performing Census Transforms that includes an input from an image, with a support window created within the image, and a kernel within the support window. The Census Transform calculations and comparisons are performed within the kernel windows. One disclosed method allows for previously performed comparison to be calculated and compared as an if not equal invert or if equal use pervious comparison hardware design. Alternatively, a new Census Transform is disclosed which always inverts a previously made comparison. This new approach can be demonstrated to be equivalent to, applying the original Census Transform, on a pre-processed input kernel, w here the pre-processing step adds a fractional position index to each pixel within the N×N kernel. The fractional positional index ensures that no two pixels are equal to one another, and thereby makes the Original Census algorithm on pre-processed kernel same as the new Census algorithm on original kernel. The hardware design for this new Census Transform kernel allows for an always invert of previous comparison system resulting in reduced hardware and power consumption. Systems and methods for performing Census Transforms that includes an input from an image, with a support window created within the image, and a kernel within the support window. The Census Transform calculations and comparisons are performed within the kernel windows. One ...more ...less
5
US20190089246A1
Publication/Patent Number: US20190089246A1
Publication date: 2019-03-21
Application number: 15/878,594
Filing date: 2018-01-24
Abstract: In some examples, a shunt regulator includes a plurality of selection pins configured to receive a digital signal. The shunt regulator also includes an internal reference voltage selection circuit coupled to the plurality of selection pins, the internal reference voltage selection circuit configured to select a first internal reference voltage of the shunt regulator based on the digital signal. The shunt regulator further includes a soft ramp control circuit coupled to the internal reference voltage selection circuit and to a soft ramp control pin that is configured to carry a second internal reference voltage, the soft ramp control circuit configured to compare the first and the second internal reference voltages to generate a soft ramp control output signal. In some examples, a shunt regulator includes a plurality of selection pins configured to receive a digital signal. The shunt regulator also includes an internal reference voltage selection circuit coupled to the plurality of selection pins, the internal reference voltage ...more ...less
6
US20190089250A1
Publication/Patent Number: US20190089250A1
Publication date: 2019-03-21
Application number: 15/707,257
Filing date: 2017-09-18
Abstract: A power converter circuit includes a power stage that includes a transformer and a switch. The switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage. The power stage includes a switching node between the switch and the primary winding having a switching voltage. The circuit also includes a switching controller configured to generate the PWM signal in response to a ramp signal. The ramp signal can have an amplitude of a slope that is proportional to a decay rate of a magnetizing current of the transformer and generated in response to feedback from the power stage. The switch can be activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal. A power converter circuit includes a power stage that includes a transformer and a switch. The switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of ...more ...less
7
US20190002025A1
Publication/Patent Number: US20190002025A1
Publication date: 2019-01-03
Application number: 15/859,280
Filing date: 2017-12-29
Abstract: A system comprises: a radio frequency (RF) resonator comprising a cavity and a tuning element, the cavity having at least one port, and the tuning element having a length inside the cavity; a processor; a spectrum analyzer coupled to the at least one port, the spectrum analyzer to provide to the processor values of a resonance parameter, the resonance parameter indicative of a resonant wavelength of the RF resonator; and an automotive steering mechanism coupled to the tuning element. A system comprises: a radio frequency (RF) resonator comprising a cavity and a tuning element, the cavity having at least one port, and the tuning element having a length inside the cavity; a processor; a spectrum analyzer coupled to the at least one port, the spectrum analyzer ...more ...less
8
US20190033434A1
Publication/Patent Number: US20190033434A1
Publication date: 2019-01-31
Application number: 15/659,919
Filing date: 2017-07-26
Abstract: An ultrasonic detection circuit includes a transmitter circuit that provides excitation signals to a terminal of an ultrasonic transducer to drive the ultrasonic transducer during an excitation interval. The excitation signals provided during the excitation interval include a first excitation signal at a first resonant frequency of the ultrasonic transducer followed by a second excitation signal at a second resonant frequency of the ultrasonic transducer. The first resonant frequency is different from the second resonant frequency. An ultrasonic detection circuit includes a transmitter circuit that provides excitation signals to a terminal of an ultrasonic transducer to drive the ultrasonic transducer during an excitation interval. The excitation signals provided during the excitation interval include a ...more ...less
9
US20190036012A1
Publication/Patent Number: US20190036012A1
Publication date: 2019-01-31
Application number: 16/147,007
Filing date: 2018-09-28
Abstract: A vertical Hall element and method of fabricating are disclosed. The method includes forming a buried region having a first conductivity type in a substrate having a second conductivity type and implanting a dopant of the first conductivity type into a well region between the top surface of the substrate and the buried region. The buried region has a doping concentration increasing with an increasing depth from a top surface of the substrate and the well region has a doping concentration decreasing from the top surface of the substrate to the buried region. The method includes forming first through fifth contacts on the well region. First and second contacts define a conductive path and second and third contacts define another conductive path through the well region. The fourth contact is formed between first and second contacts and the fifth contact is formed between second and third contacts. A vertical Hall element and method of fabricating are disclosed. The method includes forming a buried region having a first conductivity type in a substrate having a second conductivity type and implanting a dopant of the first conductivity type into a well region between the ...more ...less
10
US20190007071A1
Publication/Patent Number: US20190007071A1
Publication date: 2019-01-03
Application number: 16/125,826
Filing date: 2018-09-10
Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment. A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial ...more ...less
11
US20190020277A1
Publication/Patent Number: US20190020277A1
Publication date: 2019-01-17
Application number: 15/883,896
Filing date: 2018-01-30
Abstract: A power converter circuit includes a power stage comprising a transformer and a power switch. The power switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage. The power stage includes a switching node having a switching voltage between the power switch and the primary winding. A switching controller includes a control transistor device to initiate an operational voltage associated with the control transistor device during a startup mode of the power converter circuit and to provide a control voltage based on an amplitude of the switching voltage during a normal operating mode. The switching controller generates the PWM signal in response to comparing the control voltage and a predetermined switching threshold voltage. A power converter circuit includes a power stage comprising a transformer and a power switch. The power switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary ...more ...less
12
US20190020349A1
Publication/Patent Number: US20190020349A1
Publication date: 2019-01-17
Application number: 16/137,850
Filing date: 2018-09-21
Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle. A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired ...more ...less
13
US20190013816A1
Publication/Patent Number: US20190013816A1
Publication date: 2019-01-10
Application number: 15/859,437
Filing date: 2017-12-30
Abstract: In some examples, a system comprises an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal. The system comprises a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal. The system includes a first capacitor, coupled to the DAC, to receive the internal analog signal. The system comprises a first switch, coupled to the first capacitor, to provide the analog input signal to the first capacitor. The system comprises a second switch to couple the first capacitor to ground. In some examples, a system comprises an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal. The system comprises a digital-to-analog converter (DAC), coupled to the ADC, to ...more ...less
14
US20190013818A1
Publication/Patent Number: US20190013818A1
Publication date: 2019-01-10
Application number: 16/029,539
Filing date: 2018-07-06
Abstract: An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange). The IL mismatch estimator aggregates, during each aggregation cycle, IL mismatch estimation data based on the selected DSA active data within the DSA allocated subrange, generates an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, generates IL mismatch correction parameters based on the aggregated IL mismatch estimation data, and generates IL mismatch estimate uncertainty data corresponding to an uncertainty in the IL mismatch estimate used to generate the associated IL mismatch correction parameters for the DSA allocated subrange. A DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics). An estimation subrange allocator coupled to receive DSA setting distribution statistics, and the IL mismatch estimate uncertainty data, and to provide to the estimation subrange blanker the DSA subrange allocation signal according to a pre-defined allocation strategy. An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA ...more ...less
15
US20190018082A1
Publication/Patent Number: US20190018082A1
Publication date: 2019-01-17
Application number: 15/651,206
Filing date: 2017-07-17
Inventor: Lee, Dok Won  
Abstract: Some embodiments are directed to an anisotropic magneto-resistive (AMR) angle sensor die. The die comprises a plurality of AMR angle sensors, each of the plurality of AMR angle sensors comprising a first Wheatstone bridge and a second Wheatstone bridge, wherein an angle position output of the sensor die includes a combination of angle position outputs of each of the plurality of AMR angle sensors. Some embodiments are directed to an anisotropic magneto-resistive (AMR) angle sensor die. The die comprises a plurality of AMR angle sensors, each of the plurality of AMR angle sensors comprising a first Wheatstone bridge and a second Wheatstone bridge, wherein an angle position ...more ...less
16
US20190018107A1
Publication/Patent Number: US20190018107A1
Publication date: 2019-01-17
Application number: 15/649,413
Filing date: 2017-07-13
Abstract: An optical transmitting system for distance measuring includes a signal generator, a laser diode coupled to the signal generator, and an optics device. The signal generator is configured to generate a first plurality of electrical signals. The laser diode is configured to generate a first plurality of optical waveforms that correspond with the first plurality of electrical signals. The optics device is configured to receive the first plurality of optical waveforms and direct the first plurality of optical waveforms toward a first plurality of scan points that form a scan region within a field of view (FOV). A first signal type, a first signal duration, a first signal amplitude, or a first signal repetition frequency of the first plurality of optical waveforms is based on a first desired range of the first plurality of scan points. An optical transmitting system for distance measuring includes a signal generator, a laser diode coupled to the signal generator, and an optics device. The signal generator is configured to generate a first plurality of electrical signals. The laser diode is configured to ...more ...less
17
US20190013288A1
Publication/Patent Number: US20190013288A1
Publication date: 2019-01-10
Application number: 16/028,741
Filing date: 2018-07-06
Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space. An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface ...more ...less