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1
US10193586B1
Publication/Patent Number: US10193586B1
Publication date: 2019-01-29
Application number: 15/859,443
Filing date: 2017-12-30
Abstract: A direct conversion radio frequency receiver comprising: a clock generator to provide a first clock signal and a second clock signal; a first node; a second node; a zero-intermediate frequency (zero-IF) mixer coupled to the first and second nodes, clocked by the first and second clock signals, and comprising a first transimpedance amplifier and a second transimpedance amplifier to provide a direct-conversion voltage; a current injector, coupled to the first and second nodes, configurable to inject into the first and second nodes a common mode current or a differential mode current; and a controller, coupled to the zero-IF mixer and the current injector, to adjust at least one of the first and second transimpedance amplifiers based on the direct-conversion voltage when the current injector is to inject the common mode current. A direct conversion radio frequency receiver comprising: a clock generator to provide a first clock signal and a second clock signal; a first node; a second node; a zero-intermediate frequency (zero-IF) mixer coupled to the first and second nodes, clocked by the first and second ...more ...less
2
US10192732B2
Publication/Patent Number: US10192732B2
Publication date: 2019-01-29
Application number: 15/343,946
Filing date: 2016-11-04
Abstract: A chemical solution cleaning process for removing backside contamination prior to metallization involves selective chemistries of a mixture containing NH4OH and H2O2 that may be diluted to specific concentrations depending upon the topside metal and passivation of a semiconductor wafer, which is applied after removing a topside protection material to protect the topside circuitry. A chemical solution cleaning process for removing backside contamination prior to metallization involves selective chemistries of a mixture containing NH4OH and H2O2 that may be diluted to specific concentrations depending upon the topside metal and passivation of a ...more ...less
3
US10197623B2
Publication/Patent Number: US10197623B2
Publication date: 2019-02-05
Application number: 15/265,991
Filing date: 2016-09-15
Abstract: A contactor having the top ends of its pogo pins contacting the leads of a semiconductor device package positioned in a handler at controlled temperature, and the bottom ends of the pogo pins contacting the pads of electrically conducting vias extending vertically through a heatable interposer. The heatable interposer has a first and a second surface and includes alternating horizontal layers of thermally conductive material and thermally insulating material, and further one or more heating layers operable to control a temperature profile from the first to the second surface, including a temperature control at the first surface. The via pads at the second interposer surface are in contact with the printed circuit board of a tester. A contactor having the top ends of its pogo pins contacting the leads of a semiconductor device package positioned in a handler at controlled temperature, and the bottom ends of the pogo pins contacting the pads of electrically conducting vias extending vertically through a ...more ...less
4
US10197638B2
Publication/Patent Number: US10197638B2
Publication date: 2019-02-05
Application number: 15/186,383
Filing date: 2016-06-17
Abstract: A high bandwidth Hall sensor includes a high bandwidth path and a low bandwidth path. The relatively high offset (from sensor offset) of the high bandwidth path is estimated using a relatively low offset generated by the low bandwidth path. The relatively high offset of the high bandwidth path is substantially reduced by combining the output of the high bandwidth path with the output of the low bandwidth path to generate a high bandwidth, low offset output. The offset can be further reduced by including transimpedance amplifiers in the high bandwidth sensors to optimize the frequency response of high bandwidth Hall sensor. A high bandwidth Hall sensor includes a high bandwidth path and a low bandwidth path. The relatively high offset (from sensor offset) of the high bandwidth path is estimated using a relatively low offset generated by the low bandwidth path. The relatively high offset of the high ...more ...less
5
US10177885B1
Publication/Patent Number: US10177885B1
Publication date: 2019-01-08
Application number: 15/794,933
Filing date: 2017-10-26
Abstract: In a carrier detector, the simple latch is replaced with a pulse timer and reference control module which outputs logic high (H) when more than two consecutive toggled signals come within 1.5 baud periods and keeps logic high (H) until it misses a toggled signal for two baud periods. This carrier detector has a tolerance for a false detection which happens when the frequency shifts from lower to higher and the input amplitude level does not reach a detectable level. With this transition, the amplitude level at filter output becomes higher due to the transient response of the filter and eventually this would trigger the comparator for only one baud period. The deglitch circuit, however, ignores this clock edge in the carrier detector as provided herein. In a carrier detector, the simple latch is replaced with a pulse timer and reference control module which outputs logic high (H) when more than two consecutive toggled signals come within 1.5 baud periods and keeps logic high (H) until it misses a toggled signal for two baud ...more ...less
6
US10177136B2
Publication/Patent Number: US10177136B2
Publication date: 2019-01-08
Application number: 15/672,813
Filing date: 2017-08-09
Abstract: A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140). A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage ...more ...less
7
US10177140B2
Publication/Patent Number: US10177140B2
Publication date: 2019-01-08
Application number: 15/156,590
Filing date: 2016-05-17
Abstract: A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive electrical current from an external source. The base is configured to conduct the electrical current from the collector to the emitter. The base is disposed at the top surface of the transistor and laterally between the emitter and the collector. The collector is configured to attract and collect minority carriers from the base. The cathode of the first conductivity type is surrounded by the base and disposed between the emitter and the collector, and the cathode is configured to suppress a lateral flow of the minority carriers from the base to the collector. A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive ...more ...less
8
US10228713B1
Publication/Patent Number: US10228713B1
Publication date: 2019-03-12
Application number: 15/850,072
Filing date: 2017-12-21
Abstract: A current mirror includes a first pair of transistors, wherein gates of the first pair of transistors are connected together, and a second pair of transistors coupled to the first pair of transistors. Gates of the second pair of transistors are connected together. A first resistive device is coupled across a drain and a source of one of the transistors of the second pair of transistors. A second resistive device is coupled across a drain and a source of the other transistor of the second pair of transistors. The first pair of transistors are configured to operate in weak inversion at an input current to the current mirror within a first current range and the second pair of transistors are configured to operate in strong inversion at an input current within a second current range. A current mirror includes a first pair of transistors, wherein gates of the first pair of transistors are connected together, and a second pair of transistors coupled to the first pair of transistors. Gates of the second pair of transistors are connected together. A first ...more ...less
9
US10230928B2
Publication/Patent Number: US10230928B2
Publication date: 2019-03-12
Application number: 14/921,438
Filing date: 2015-10-23
Abstract: An image may be formed in a projection system by forming a light beam with substantially a first polarization. The light beam is directed onto a first color wheel that transmits a first selected color portion of the light beam and reflects a second color portion of the light beam. The reflected second color portion is converted to a second polarization. A first portion of the image is produced with a first spatial light modulator using the first selected color portion of the light beam having the first polarization. A second portion of the image is produced with a second spatial light modulator using at least a portion of the reflected second color portion of the light beam having the second polarization. The first portion of the image and the second portion of the image are combined to form a combined image for projection. An image may be formed in a projection system by forming a light beam with substantially a first polarization. The light beam is directed onto a first color wheel that transmits a first selected color portion of the light beam and reflects a second color portion of the light ...more ...less
10
US10263085B2
Publication/Patent Number: US10263085B2
Publication date: 2019-04-16
Application number: 15/415,995
Filing date: 2017-01-26
Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings. A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a ...more ...less
11
US10284077B1
Publication/Patent Number: US10284077B1
Publication date: 2019-05-07
Application number: 15/785,757
Filing date: 2017-10-17
Abstract: A Power Factor Correction (PFC) controller includes an error amplifier for amplifying a difference between Vout and intended Vout to provide a power demand (Pdem) output at a compensation pin. A burst mode controller includes soft-start circuitry coupled to receive Pdem and to a drive pin which provides pulses to a control node of a power switch of a DC-DC converter during burst periods. The pulses slow ramping of line current over a first 2 to 36 switching cycles at a beginning of bursts when energizing the inductor to reduce a line current slope as compared to without ramping up, and for slowing ramping down of line current over the last 2 to 36 switching cycles to reduce a line current slope when de-energizing the inductor as compared to a line current without ramping down. The PFC controller does not utilize zero-crossings of the line voltage for burst period synchronization. A Power Factor Correction (PFC) controller includes an error amplifier for amplifying a difference between Vout and intended Vout to provide a power demand (Pdem) output at a compensation pin. A burst mode controller includes soft-start circuitry coupled to receive Pdem and to a ...more ...less
12
US10291228B1
Publication/Patent Number: US10291228B1
Publication date: 2019-05-14
Application number: 15/973,766
Filing date: 2018-05-08
Inventor: Finn, Steven Ernest  
Abstract: A driver circuit includes a first termination resistor and a distributed amplifier comprising a plurality of pairs of input transistors and comprising inductors coupled between each pair of input transistors. The driver circuit also includes a distributed current-mode level shifter coupled to the first termination resistor. The distributed current-mode level shifter includes a first plurality of inductors coupled in series between the first termination resistor and the distributed amplifier and a first plurality of capacitive devices. Each capacitive device is coupled to a power supply node and to a node interconnecting two of the series-coupled inductors. A driver circuit includes a first termination resistor and a distributed amplifier comprising a plurality of pairs of input transistors and comprising inductors coupled between each pair of input transistors. The driver circuit also includes a distributed current-mode level ...more ...less
13
US10236902B1
Publication/Patent Number: US10236902B1
Publication date: 2019-03-19
Application number: 15/874,100
Filing date: 2018-01-18
Abstract: An analog-to-digital converter includes an input terminal, a digital-to-analog converter, a comparator, and successive approximation circuitry. The input terminal is configured to receive a multi-bit digital threshold value from circuitry external to the analog-to-digital converter. The successive approximation circuitry is coupled to the comparator and the digital-to-analog converter. The successive approximation circuitry is configured to operate in a comparison mode and a conversion mode, and to provide the multi-bit digital threshold value to the digital-to-analog converter while operating in the comparison mode. The comparator is coupled to the digital-to-analog converter and the successive approximation circuitry. The comparator is configured to output a signal that indicates whether an analog input signal exceeds an analog threshold signal corresponding to the multi-bit digital threshold value. An analog-to-digital converter includes an input terminal, a digital-to-analog converter, a comparator, and successive approximation circuitry. The input terminal is configured to receive a multi-bit digital threshold value from circuitry external to the analog-to-digital ...more ...less
14
US10248872B2
Publication/Patent Number: US10248872B2
Publication date: 2019-04-02
Application number: 15/298,218
Filing date: 2016-10-19
Abstract: A method for estimating time to collision (TTC) of a detected object in a computer vision system is provided that includes determining a three dimensional (3D) position of a camera in the computer vision system, determining a 3D position of the detected object based on a 2D position of the detected object in an image captured by the camera and an estimated ground plane corresponding to the image, computing a relative 3D position of the camera, a velocity of the relative 3D position, and an acceleration of the relative 3D position based on the 3D position of the camera and the 3D position of the detected object, wherein the relative 3D position of the camera is relative to the 3D position of the detected object, and computing the TTC of the detected object based on the relative 3D position, the velocity, and the acceleration. A method for estimating time to collision (TTC) of a detected object in a computer vision system is provided that includes determining a three dimensional (3D) position of a camera in the computer vision system, determining a 3D position of the detected object based on a 2D ...more ...less
15
US10243464B2
Publication/Patent Number: US10243464B2
Publication date: 2019-03-26
Application number: 15/854,061
Filing date: 2017-12-26
Abstract: A controller including a voltage synthesizer for a switching regulator includes a synthesizer input to be coupled to an input of the regulator. First and second replica switching transistors are connected at a first node. A resistor couples between the first node and a second node, and a capacitor couples between the second node and ground. A transconductance stage compares a voltage sampled onto the capacitor to the output voltage of the regulator and generates an output signal in response to the comparison. A first switch couples between first and second inputs of the transconductance stage. The first switch is turned on during each cycle of operation of the voltage synthesizer to reset the capacitor voltage to the output voltage of the regulator. A controller including a voltage synthesizer for a switching regulator includes a synthesizer input to be coupled to an input of the regulator. First and second replica switching transistors are connected at a first node. A resistor couples between the first node and a second ...more ...less
16
US10250211B1
Publication/Patent Number: US10250211B1
Publication date: 2019-04-02
Application number: 15/807,927
Filing date: 2017-11-09
Inventor: Singh, Ravpreet  
Abstract: Reducing non-linear distortions of an electronic device by performing at least the following: receiving, at an output stage circuit of an amplifier, an input signal from a previous stage circuit of the amplifier, driving a first subset of output transistors within the output stage circuit with an auxiliary buffer circuit to generate a first half cycle of an output signal Vout, driving a second subset of output transistors within the output stage circuit with the input signal to generate the first half cycle of the output signal Vout, and driving a set of output transistors with the input signal to generate a second half cycle of the output signal Vout, wherein the auxiliary buffer circuit equalizes the overall current gain associated with the first and second subset of output transistors with the overall current gain associated with the set of output transistors. Reducing non-linear distortions of an electronic device by performing at least the following: receiving, at an output stage circuit of an amplifier, an input signal from a previous stage circuit of the amplifier, driving a first subset of output transistors within the output ...more ...less
17
US10250253B2
Publication/Patent Number: US10250253B2
Publication date: 2019-04-02
Application number: 15/996,994
Filing date: 2018-06-04
Abstract: The disclosure provides a detector that includes a pre-charge circuit. The pre-charge circuit receives a supply voltage. A pre-charged comparator is coupled to the pre-charge circuit and receives the supply voltage. The pre-charged comparator generates a transition signal at a transition node. A slope of the transition signal is greater than a slope of the supply voltage. A first diode connected transistor receives the supply voltage. A first capacitor is coupled to the first diode connected transistor. An inverter is coupled to the first diode connected transistor and generates an enable signal when the supply voltage is below a threshold voltage. The disclosure provides a detector that includes a pre-charge circuit. The pre-charge circuit receives a supply voltage. A pre-charged comparator is coupled to the pre-charge circuit and receives the supply voltage. The pre-charged comparator generates a transition signal at a ...more ...less
18
US10276684B2
Publication/Patent Number: US10276684B2
Publication date: 2019-04-30
Application number: 15/372,512
Filing date: 2016-12-08
Abstract: An integrated circuit may include a metal gate which extends over an active area and onto an isolation dielectric layer. A conductive spline is formed on the metal gate, extending on the metal gate over at least a portion of the isolation dielectric layer, and extending on the metal gate for a length at least four times a width of the metal gate. An integrated circuit may include a metal gate which extends over an active area and onto an isolation dielectric layer. A conductive spline is formed on the metal gate, extending on the metal gate over at least a portion of the isolation dielectric layer, and extending on the ...more ...less
19
US10276787B2
Publication/Patent Number: US10276787B2
Publication date: 2019-04-30
Application number: 15/041,575
Filing date: 2016-02-11
Abstract: An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads. An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and ...more ...less