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1
US9287292B2
Publication/Patent Number: US9287292B2
Publication date: 2016-03-15
Application number: 27/783,308
Filing date: 2008-11-25
Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support ...more ...less
2
US9287400B2
Publication/Patent Number: US9287400B2
Publication date: 2016-03-15
Application number: 20/121,358
Filing date: 2012-08-16
Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in ...more ...less
3
WO2013030935A1
Publication/Patent Number: WO2013030935A1
Publication date: 2013-03-07
Application number: 2011069490
Filing date: 2011-08-29
Abstract: In this solar cell
4
WO2013021906A1
Publication/Patent Number: WO2013021906A1
Publication date: 2013-02-14
Application number: 2012069689
Filing date: 2012-08-02
Abstract: Provided is a piezoelectric sound element capable of flattening a sound pressure frequency property and reducing variation in the sound pressure frequency property
5
US20120318337A1
Publication/Patent Number: US20120318337A1
Publication date: 2012-12-20
Application number: 13/521,487
Filing date: 2012-02-17
Abstract: In a conventional solar cell, it has been difficult to ensure a sufficient light absorption and simultaneously to prevent current loss due to the reduction of the moving distance of electrons and holes. As a means for solving this difficulty, a plurality of a p-i-n junctions are stacked through an insulating film and are connected in parallel with each other using through-electrodes. In this case, the through-electrodes and the p-i-n junctions are connected through the p-layer or the n-layer, thereby moving electrons and holes in opposite directions and generating output current. In addition, the i-layer is made thicker than the p-layer and the n-layer in each of the p-i-n junctions, thereby ensuring a sufficient light absorption and simultaneously preventing current loss. In a conventional solar cell, it has been difficult to ensure a sufficient light absorption and simultaneously to prevent current loss due to the reduction of the moving distance of electrons and holes. As a means for solving this difficulty, a plurality of a p-i-n junctions are ...more ...less
6
US20120309157A1
Publication/Patent Number: US20120309157A1
Publication date: 2012-12-06
Application number: 13/587,361
Filing date: 2012-08-16
Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable. An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in ...more ...less
7
WO2012160662A1
Publication/Patent Number: WO2012160662A1
Publication date: 2012-11-29
Application number: 2011061955
Filing date: 2011-05-25
Abstract: A solar cell comprising a substrate (1)
8
US7959120B2
Publication/Patent Number: US7959120B2
Publication date: 2011-06-14
Application number: 12/340,535
Filing date: 2008-12-19
Inventor: Liao, Chin-hui  
Abstract: A universal support is provided in the present invention. The universal support includes a brace unit, a mounting unit and a connecting unit, in which the brace unit has several joint assemblies with stronger mechanical strength and several quick-release clamp unit to carry heavier load, while the connecting unit can be securely fastened to a stationary object and the mounting unit can perform universally rotation so as to perfectly satisfy every need of the users. A universal support is provided in the present invention. The universal support includes a brace unit, a mounting unit and a connecting unit, in which the brace unit has several joint assemblies with stronger mechanical strength and several quick-release clamp unit to carry ...more ...less
9
WO2011118298A1
Publication/Patent Number: WO2011118298A1
Publication date: 2011-09-29
Application number: 2011053398
Filing date: 2011-02-17
Abstract: In a conventional solar cell
10
US20100084709A1
Publication/Patent Number: US20100084709A1
Publication date: 2010-04-08
Application number: 11/993,862
Filing date: 2006-06-30
Abstract: When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common. When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate ...more ...less
11
WO2010082498A1
Publication/Patent Number: WO2010082498A1
Publication date: 2010-07-22
Application number: 2010000200
Filing date: 2010-01-15
Abstract: Disclosed is an excellently reliable technique which enables control of the threshold voltage of a field effect transistor after the production of an LSI
12
US7812398B2
Publication/Patent Number: US7812398B2
Publication date: 2010-10-12
Application number: 40/032,409
Filing date: 2009-03-09
Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased
13
WO2010082504A1
Publication/Patent Number: WO2010082504A1
Publication date: 2010-07-22
Application number: 2010000236
Filing date: 2010-01-18
Abstract: Disclosed is an SOI-MISFET having excellent characteristics of low power consumption and high speed operation
14
US20090096036A1
Publication/Patent Number: US20090096036A1
Publication date: 2009-04-16
Application number: 12/248,250
Filing date: 2008-10-09
Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided. There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the ...more ...less
15
US20090261412A1
Publication/Patent Number: US20090261412A1
Publication date: 2009-10-22
Application number: 12/400,324
Filing date: 2009-03-09
Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI. A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon ...more ...less
16
WO2008120346A1
Publication/Patent Number: WO2008120346A1
Publication date: 2008-10-09
Application number: 2007056830
Filing date: 2007-03-29
Abstract: When a low-order module is bottomed up to a high-order module
17
US20080017904A1
Publication/Patent Number: US20080017904A1
Publication date: 2008-01-24
Application number: 11/773,990
Filing date: 2007-07-06
Abstract: A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured. A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the ...more ...less