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1
US10258436B2
Publication/Patent Number: US10258436B2
Publication date: 2019-04-16
Application number: 14/739,556
Filing date: 2015-06-15
Abstract: This invention discloses a physical gateway that goes directly through gum or other soft tissues inside the oral cavity, to access inside body. The physical gateway has parts acting as external access points that have terminals for cables, wires, fiber optics, or tubes that go through said gateways to implanted medical systems and devices to facilitate transmission of signals or materials to or from said implanted systems or devices. This feature can be used for powering implanted systems and devices with high functionality and computation power, securely communicating with implanted systems and devices with vital duties, and transferring materials for refilling the tanks in implanted systems and devices or for transferring some material from inside body to outside without requiring invasive operations. This invention discloses a physical gateway that goes directly through gum or other soft tissues inside the oral cavity, to access inside body. The physical gateway has parts acting as external access points that have terminals for cables, wires, fiber optics, or tubes that go ...more ...less
2
US2015374462A1
Publication/Patent Number: US2015374462A1
Publication date: 2015-12-31
Application number: 14/739,556
Filing date: 2015-06-15
Abstract: This invention discloses a physical gateway that goes directly through gum or other soft tissues inside the oral cavity, to access inside body. The physical gateway has parts acting as external access points that have terminals for cables, wires, fiber optics, or tubes that go through said gateways to implanted medical systems and devices to facilitate transmission of signals or materials to or from said implanted systems or devices. This feature can be used for powering implanted systems and devices with high functionality and computation power, securely communicating with implanted systems and devices with vital duties, and transferring materials for refilling the tanks in implanted systems and devices or for transferring some material from inside body to outside without requiring invasive operations. This invention discloses a physical gateway that goes directly through gum or other soft tissues inside the oral cavity, to access inside body. The physical gateway has parts acting as external access points that have terminals for cables, wires, fiber optics, or tubes that go ...more ...less
3
US8898537B2
Publication/Patent Number: US8898537B2
Publication date: 2014-11-25
Application number: 13/050,065
Filing date: 2011-03-17
Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error correction performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with the code length. They also offer challenges relating to the decoding complexity of the binary error-correction codes themselves and error floors limiting achievable bit-error rates. A new Relaxed Half-Stochastic (RHS) decoding algorithm is presented that reduces decoding complexity for high decoding throughput applications. The RHS algorithm uses an approach based on stochastic decoding algorithms but differs significantly from the conventional approaches of LDPC decoder implementation. The RHS algorithm also leads to a randomized decoding technique called redecoding that addresses the error floor limitation. Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error ...more ...less
4
US8677227B2
Publication/Patent Number: US8677227B2
Publication date: 2014-03-18
Application number: 13/216,373
Filing date: 2011-08-24
Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates. Accordingly encoders with reduced complexity, reduced power consumption and improved performance are disclosed with various improvements including simplifying communications linking multiple processing nodes by passing messages where pulse widths are modulated with the corresponding message magnitude, delaying a check operation in dependence upon variable node states, running the decoder multiple times with different random number generator seeds for a constant channel value set, and employing a second decoder with a randomizing component when the attempt with the first decoder fails. Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance ...more ...less
5
US2012054576A1
Publication/Patent Number: US2012054576A1
Publication date: 2012-03-01
Application number: 13/216,373
Filing date: 2011-08-24
Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates. Accordingly encoders with reduced complexity, reduced power consumption and improved performance are disclosed with various improvements including simplifying communications linking multiple processing nodes by passing messages where pulse widths are modulated with the corresponding message magnitude, delaying a check operation in dependence upon variable node states, running the decoder multiple times with different random number generator seeds for a constant channel value set, and employing a second decoder with a randomizing component when the attempt with the first decoder fails. Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance ...more ...less
6
US2011231731A1
Publication/Patent Number: US2011231731A1
Publication date: 2011-09-22
Application number: 13/050,065
Filing date: 2011-03-17
Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error correction performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with the code length. They also offer challenges relating to the decoding complexity of the binary error-correction codes themselves and error floors limiting achievable bit-error rates. A new Relaxed Half-Stochastic (RHS) decoding algorithm is presented that reduces decoding complexity for high decoding throughput applications. The RHS algorithm uses an approach based on stochastic decoding algorithms but differs significantly from the conventional approaches of LDPC decoder implementation. The RHS algorithm also leads to a randomized decoding technique called redecoding that addresses the error floor limitation. Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error ...more ...less
7
US7769798B2
Publication/Patent Number: US7769798B2
Publication date: 2010-08-03
Application number: 10/832,806
Filing date: 2004-04-27
Abstract: Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. Soft information is passed among variable nodes and parity-check nodes. A low-voltage high-swing Max WTA circuit is also provided. The circuit can be implemented by short channel MOSFET transistors and yet provide a reasonably high degree of accuracy. Applications include soft computing, and analog signal processing, in general. A Min WTA circuit can also be built based on this circuit by subtracting the input currents from a large reference current. Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo ...more ...less
8
US2005240647A1
Publication/Patent Number: US2005240647A1
Publication date: 2005-10-27
Application number: 10/832,806
Filing date: 2004-04-27
Abstract: Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. Soft information is passed among variable nodes and parity-check nodes. A low-voltage high-swing Max WTA circuit is also provided. The circuit can be implemented by short channel MOSFET transistors and yet provide a reasonably high degree of accuracy. Applications include soft computing, and analog signal processing, in general. A Min WTA circuit can also be built based on this circuit by subtracting the input currents from a large reference current. Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo ...more ...less