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1
US20190045664A1
Publication/Patent Number: US20190045664A1
Publication date: 2019-02-07
Application number: 15/855,545
Filing date: 2017-12-27
Abstract: An electronic device is provided. The electronic device includes a heat source, a heat-conductive member and a heat-dissipating sheet. The heat-conductive member includes a recess, wherein the recess is thermally connected to the heat source. The heat-dissipating sheet is attached to the heat-conductive member, wherein the heat-dissipating sheet covers the recess. An electronic device is provided. The electronic device includes a heat source, a heat-conductive member and a heat-dissipating sheet. The heat-conductive member includes a recess, wherein the recess is thermally connected to the heat source. The heat-dissipating sheet is ...more ...less
2
US20190130990A1
Publication/Patent Number: US20190130990A1
Publication date: 2019-05-02
Application number: 16/159,045
Filing date: 2018-10-12
Abstract: A method for testing firmware of an SSD includes: controlling a main memory to emulate volatile and non-volatile memories of the SSD, fetching a testing sequence and a testing criterion, fetching read/write operations from binary codes generated by compiling the firmware, determining whether the read/write operations are associated with a marker, executing the read/write operations when a result of determination is affirmative, otherwise discarding a read/write of data, monitoring whether processes of executing of the read/write operations meet the testing criterion, and generating a result of a test of the firmware when it is monitored that the testing criterion is met. A method for testing firmware of an SSD includes: controlling a main memory to emulate volatile and non-volatile memories of the SSD, fetching a testing sequence and a testing criterion, fetching read/write operations from binary codes generated by compiling the firmware ...more ...less
3
US20190139491A1
Publication/Patent Number: US20190139491A1
Publication date: 2019-05-09
Application number: 15/952,252
Filing date: 2018-04-13
Abstract: A driving control circuit with a compensating circuit detects pixel driving circuits in a display apparatus for compensating a threshold voltage in the pixel driving circuits. The compensating circuit electrically connects with the pixel driving circuits through a corresponding monitoring line. The pixel driving circuit sequentially operates during a detecting time period and a displaying period. Each pixel driving circuit comprises a driving transistor and an OLED. During the detecting time period, the compensating circuit charges a node in each pixel driving circuit by a constant current for speeding up a time of the detecting time period. The node is connected between a terminal of the driving transistor and the OLED in each pixel driving circuit. A driving control circuit with a compensating circuit detects pixel driving circuits in a display apparatus for compensating a threshold voltage in the pixel driving circuits. The compensating circuit electrically connects with the pixel driving circuits through a corresponding ...more ...less
4
US20190139492A1
Publication/Patent Number: US20190139492A1
Publication date: 2019-05-09
Application number: 15/952,254
Filing date: 2018-04-13
Abstract: A driving control system for driving pixel driving circuits in a display apparatus includes a selecting module, a compensating circuit, and a controller. The pixel driving circuit sequentially operates during a detecting time period and a displaying period. Each pixel driving circuit comprises a driving transistor and an OLED. During the detecting time period, the selecting circuit selects at least one of the pixel driving circuits, the driving transistor in the selected at least one of the pixel driving circuits becomes saturated, the compensating circuit detects a detecting current of the selected pixel driving circuit and converts the detecting current into a specified parameter, the controller adjusts a driving voltage provided to the selected pixel driving circuit based on the specified parameter. A driving control system for driving pixel driving circuits in a display apparatus includes a selecting module, a compensating circuit, and a controller. The pixel driving circuit sequentially operates during a detecting time period and a displaying period. Each pixel driving ...more ...less
5
US10319581B1
Publication/Patent Number: US10319581B1
Publication date: 2019-06-11
Application number: 15/827,709
Filing date: 2017-11-30
Abstract: A method includes providing a structure having a substrate and first and second fins over the substrate and oriented lengthwise generally along a first direction; epitaxially growing semiconductor source/drain (S/D) features over the first and second fins, wherein a first semiconductor S/D feature over the first fin merges with a second semiconductor S/D feature over the second fin; and performing a first etching process to an area between the first and second fins, wherein the first etching process separates the first and second semiconductor S/D features. A method includes providing a structure having a substrate and first and second fins over the substrate and oriented lengthwise generally along a first direction; epitaxially growing semiconductor source/drain (S/D) features over the first and second fins, wherein a first ...more ...less
6
US20190157159A1
Publication/Patent Number: US20190157159A1
Publication date: 2019-05-23
Application number: 15/816,155
Filing date: 2017-11-17
Abstract: A device that includes a substrate; semiconductor fins extending from the substrate; an isolation structure over the substrate and laterally between the semiconductor fins; a liner layer between sidewalls of the semiconductor fins and the isolation structure; and an etch stop layer between the substrate and the isolation structure and laterally between the semiconductor fins. The etch stop layer includes a material different than that of the isolation structure and the liner layer. A device that includes a substrate; semiconductor fins extending from the substrate; an isolation structure over the substrate and laterally between the semiconductor fins; a liner layer between sidewalls of the semiconductor fins and the isolation structure; and an etch stop ...more ...less
7
US20190164741A1
Publication/Patent Number: US20190164741A1
Publication date: 2019-05-30
Application number: 15/827,709
Filing date: 2017-11-30
Abstract: A method includes providing a structure having a substrate and first and second fins over the substrate and oriented lengthwise generally along a first direction; epitaxially growing semiconductor source/drain (S/D) features over the first and second fins, wherein a first semiconductor S/D feature over the first fin merges with a second semiconductor S/D feature over the second fin; and performing a first etching process to an area between the first and second fins, wherein the first etching process separates the first and second semiconductor S/D features. A method includes providing a structure having a substrate and first and second fins over the substrate and oriented lengthwise generally along a first direction; epitaxially growing semiconductor source/drain (S/D) features over the first and second fins, wherein a first ...more ...less
8
US20190067104A1
Publication/Patent Number: US20190067104A1
Publication date: 2019-02-28
Application number: 15/801,000
Filing date: 2017-11-01
Abstract: An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die. An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first ...more ...less
9
US20190031917A1
Publication/Patent Number: US20190031917A1
Publication date: 2019-01-31
Application number: 16/046,423
Filing date: 2018-07-26
Abstract: A method of forming a thermal insulation porous film includes mixing 100 parts by weight of polysilsesquioxane-containing polymer, 20 to 75 parts by weight of surfactant, and 20 to 2000 parts by weight of solvent to form a thermal insulation coating material, wherein the polysilsesquioxane-containing polymer in the thermal insulation coating material is tube-shaped or sheet-shaped. The thermal insulation coating material is coated on a substrate, and then dried and sintered to form a thermal insulation porous film. A method of forming a thermal insulation porous film includes mixing 100 parts by weight of polysilsesquioxane-containing polymer, 20 to 75 parts by weight of surfactant, and 20 to 2000 parts by weight of solvent to form a thermal insulation coating material, wherein the ...more ...less
10
US20190157240A1
Publication/Patent Number: US20190157240A1
Publication date: 2019-05-23
Application number: 16/028,813
Filing date: 2018-07-06
Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first ...more ...less
11
US10170536B1
Publication/Patent Number: US10170536B1
Publication date: 2019-01-01
Application number: 15/626,686
Filing date: 2017-06-19
Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a magnetic layer in the second passivation layer; and an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide. A method for manufacturing a semiconductor structure is also disclosed. A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a magnetic layer in the second passivation layer; and an etch stop layer between ...more ...less
12
US20190189496A1
Publication/Patent Number: US20190189496A1
Publication date: 2019-06-20
Application number: 16/224,811
Filing date: 2018-12-19