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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10635528B2
Memory controller and method of controlling memory controller
Publication/Patent Number: US10635528B2 Publication Date: 2020-04-28 Application Number: 15/323,574 Filing Date: 2015-05-20 Inventor: Shinbashi, Tatsuo   Sakai, Lui   Ikegaya, Ryoji   Assignee: SONY CORPORATION   IPC: G11C29/52 Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data. A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell ...More ...Less
2 US2017147433A1
MEMORY CONTROLLER AND METHOD OF CONTROLLING MEMORY CONTROLLER
Publication/Patent Number: US2017147433A1 Publication Date: 2017-05-25 Application Number: 15/323,574 Filing Date: 2015-05-20 Inventor: Shinbashi, Tatsuo   Sakai, Lui   Ikegaya, Ryoji   Assignee: SONY CORPORATION   IPC: G06F11/10 Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data. A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell ...More ...Less
3 US9608668B2
Error correcting apparatus, error correcting method, and program
Publication/Patent Number: US9608668B2 Publication Date: 2017-03-28 Application Number: 14/528,555 Filing Date: 2014-10-30 Inventor: Ikegaya, Ryoji   Shinbashi, Tatsuo   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: H03M13/00 Abstract: Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a predetermined condition, the received word having a plurality of symbols, the determination process including determining if a determination-target symbol has an error or not, and detecting an error position, the error position being a position of the symbol having an error; changing, by a determination-target changing unit, the position of the determination-target symbol of the received word every time the determination process is executed; detecting, by an undetected-position detector, if the predetermined condition is satisfied, the error position of the symbol, for which the determination process is not executed, based on a relation between the error position and a variable generated from the received word; and correcting, by an error corrector, an error at the error position detected by the error-position detector and the undetected-position detector. Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a predetermined condition, the received word having a plurality of symbols, the determination process including determining if ...More ...Less
4 WO2016013285A1
MEMORY CONTROLLER AND METHOD FOR CONTROLLING MEMORY CONTROLLER
Publication/Patent Number: WO2016013285A1 Publication Date: 2016-01-28 Application Number: 2015064448 Filing Date: 2015-05-20 Inventor: Sakai, Lui   Shinbashi, Tatsuo   Ikegaya, Ryoji   Assignee: Sony Corporation   IPC: G06F12/16 Abstract: The objective of the present technology is to improve the usage efficiency of a memory. An encoded word generation unit generates an encoded word from data to be encoded in error detection/correction encoding. A write processing unit writes to a memory cell
5 US9417956B2
Error detection and correction unit, error detection and correction method, information processor, and program
Publication/Patent Number: US9417956B2 Publication Date: 2016-08-16 Application Number: 14/154,918 Filing Date: 2014-01-14 Inventor: Sakai, Lui   Ikegaya, Ryoji   Shinbashi, Tatsuo   Nakanishi, Kenichi   Fujinami, Yasushi   Yamamoto, Makiko   Assignee: Sony Corporation   IPC: H03M13/00 Abstract: An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data. An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in ...More ...Less
6 US9280455B2
Memory control device, non-volatile memory, and memory control method
Publication/Patent Number: US9280455B2 Publication Date: 2016-03-08 Application Number: 13/945,987 Filing Date: 2013-07-19 Inventor: Adachi, Naohiro   Tsutsui, Keiichi   Ishii, Ken   Okubo, Hideaki   Nakanishi, Kenichi   Fujinami, Yasushi   Shinbashi, Tatsuo   Sakai, Lui   Ikegaya, Ryoji   Assignee: SONY CORPORATION   IPC: G06F12/02 Abstract: Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written. Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not ...More ...Less
7 US2015155885A1
ERROR CORRECTING APPARATUS, ERROR CORRECTING METHOD, AND PROGRAM
Publication/Patent Number: US2015155885A1 Publication Date: 2015-06-04 Application Number: 14/528,555 Filing Date: 2014-10-30 Inventor: Ikegaya, Ryoji   Shinbashi, Tatsuo   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: H03M13/15 Abstract: Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a predetermined condition, the received word having a plurality of symbols, the determination process including determining if a determination-target symbol has an error or not, and detecting an error position, the error position being a position of the symbol having an error; changing, by a determination-target changing unit, the position of the determination-target symbol of the received word every time the determination process is executed; detecting, by an undetected-position detector, if the predetermined condition is satisfied, the error position of the symbol, for which the determination process is not executed, based on a relation between the error position and a variable generated from the received word; and correcting, by an error corrector, an error at the error position detected by the error-position detector and the undetected-position detector. Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a predetermined condition, the received word having a plurality of symbols, the determination process including determining if ...More ...Less
8 US9110827B2
Error detection and correction apparatus, mismatch detection apparatus, memory system and error detection and correction method
Publication/Patent Number: US9110827B2 Publication Date: 2015-08-18 Application Number: 14/049,248 Filing Date: 2013-10-09 Inventor: Sakai, Lui   Fujinami, Yasushi   Adachi, Naohiro   Tsutsui, Keiichi   Shinbashi, Tatsuo   Ikegaya, Ryoji   Assignee: Sony Corporation   IPC: H03M13/00 Abstract: An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected. An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to ...More ...Less