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1
US20190043949A1
Publication/Patent Number: US20190043949A1
Publication date: 2019-02-07
Application number: 16/150,323
Filing date: 2018-10-03
Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode. Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the ...more ...less
2
US20190006471A1
Publication/Patent Number: US20190006471A1
Publication date: 2019-01-03
Application number: 16/066,777
Filing date: 2016-11-28
Abstract: A silicon carbide semiconductor device includes: an n-type drift layer 2 provided within an SiC layer 30; a plurality of p-type well regions 3; a JFET region JR serving as a part of the drift layer 2 sandwiched between the well regions 3; and a gate insulating film 6 and a gate electrode 7 at least covering the JFET region JR. The gate insulating film 6 and the gate electrode 7 include a different-element-containing region 10 containing an element that is different from elements constituting the gate insulating film 6 and the gate electrode 7. A silicon carbide semiconductor device includes: an n-type drift layer 2 provided within an SiC layer 30; a plurality of p-type well regions 3; a JFET region JR serving as a part of the drift layer 2 sandwiched between the well regions 3; and a gate insulating film 6 and a gate ...more ...less
3
US10263078B2
Publication/Patent Number: US10263078B2
Publication date: 2019-04-16
Application number: 15/925,850
Filing date: 2018-03-20
Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode. Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the ...more ...less
4
US20190131388A1
Publication/Patent Number: US20190131388A1
Publication date: 2019-05-02
Application number: 16/307,184
Filing date: 2017-05-23
Abstract: The technique disclosed in the Description relates to a technique preventing dielectric breakdown while a silicon carbide semiconductor device is OFF, without degrading process throughput or yield. The silicon carbide semiconductor device relating to the technique disclosed in the Description includes a drift layer of a first conductivity type, a threading dislocation provided to penetrate the drift layer, and an electric-field reduction region of a second conductivity type disposed in a position in the surface layer of the drift layer, the position corresponding to the threading dislocation. The electric-field reduction region is an epitaxial layer. The technique disclosed in the Description relates to a technique preventing dielectric breakdown while a silicon carbide semiconductor device is OFF, without degrading process throughput or yield. The silicon carbide semiconductor device relating to the technique disclosed in ...more ...less
5
WO2018012241A1
Publication/Patent Number: WO2018012241A1
Publication date: 2018-01-18
Application number: 2017023023
Filing date: 2017-06-22
Abstract: The present invention relates to a semiconductor device and is provided with: a first semiconductor layer which is disposed on a first main surface of a semiconductor substrate; a plurality of first semiconductor regions which are selectively formed in the upper part of the semiconductor layer; second semiconductor regions which are selectively formed in the upper parts of the first semiconductor regions; a second semiconductor layer which is disposed on a JFET region that is a region of the first semiconductor layer between the first semiconductor regions The present invention relates to a semiconductor device and is provided with: a first semiconductor layer which is disposed on a first main surface of a semiconductor substrate; a plurality of first semiconductor regions which are selectively formed in the upper part of the ...more ...less
6
JP6262060B2
Publication/Patent Number: JP6262060B2
Publication date: 2018-01-17
Application number: 2014076974
Filing date: 2014-04-03
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method and a semiconductor device
7
JP2018061468A
Publication/Patent Number: JP2018061468A
Publication date: 2018-04-19
Application number: 2016201107
Filing date: 2016-10-12
Abstract: PROBLEM TO BE SOLVED: To provide a plowing claw capable of reducing power requirement.SOLUTION: A plowing claw 35 comprises a mounting base 41, a vertical blade part 42, and a horizontal blade part 43. The vertical and horizontal blade parts 42 and 43 have a blade edge part 46 and a peak edge part 47. A tangent line B in a horizontal peak edge tip position b is inclined to a tip side at a tilt angle α larger than 0 degree and smaller than or equal to 60 degrees with respect to a vertical line C in a side view in a state in which the plowing claw is mounted so that a vertical blade edge tip position a can be a lowermost position.SELECTED DRAWING: Figure 2 PROBLEM TO BE SOLVED: To provide a plowing claw capable of reducing power requirement.SOLUTION: A plowing claw 35 comprises a mounting base 41, a vertical blade part 42, and a horizontal blade part 43. The vertical and horizontal blade parts 42 and 43 have a blade edge part 46 ...more ...less
8
JP2018061469A
Publication/Patent Number: JP2018061469A
Publication date: 2018-04-19
Application number: 2016201108
Filing date: 2016-10-12
Abstract: PROBLEM TO BE SOLVED: To provide a plowing claw capable of improving clod breaking and inversion performance.SOLUTION: A plowing claw 35 comprises a mounting base 41, a vertical blade part 42, and a horizontal blade part 43. The vertical and horizontal blade parts 42 and 43 have a blade edge part 46 and a peak edge part 47. A tangent line B in a horizontal peak edge tip position b is inclined to a base end side at a tilt angle α larger than 0 degree and smaller than or equal to 15 degrees with respect to a vertical line C in a side view in a state in which the plowing claw is mounted so that a vertical blade edge tip position a can be a lowermost position.SELECTED DRAWING: Figure 2 PROBLEM TO BE SOLVED: To provide a plowing claw capable of improving clod breaking and inversion performance.SOLUTION: A plowing claw 35 comprises a mounting base 41, a vertical blade part 42, and a horizontal blade part 43. The vertical and horizontal blade parts 42 and 43 have ...more ...less
9
JP6258672B2
Publication/Patent Number: JP6258672B2
Publication date: 2018-01-10
Application number: 2013240906
Filing date: 2013-11-21
Abstract: PROBLEM TO BE SOLVED: To suppress deterioration in performance of a semiconductor device.SOLUTION: When a width of an active region ACT1 where a field-effect transistor Q1 is formed is smaller than that of an active region ACT2 where a field-effect transistor Q2 is formed
10
JP2018033443A
Publication/Patent Number: JP2018033443A
Publication date: 2018-03-08
Application number: 2017078765
Filing date: 2017-04-12
Abstract: PROBLEM TO BE SOLVED: To provide an agricultural implement capable of reducing a load of an operator.SOLUTION: An agricultural implement 1 includes a machine body 2 connected to a tractor. A leveling body 4 is provided on the machine body 2 rotatably in the vertical direction. Lifting assist means 8 for assisting lifting of the leveling body 4 is provided between the machine body 2 and the leveling body 4. The lifting assist means 8 has a U-shaped frame-like long body 36 opened toward the lower side. A plurality of gas springs 32 are stored in the U-shaped frame-like long body 36.SELECTED DRAWING: Figure 1 PROBLEM TO BE SOLVED: To provide an agricultural implement capable of reducing a load of an operator.SOLUTION: An agricultural implement 1 includes a machine body 2 connected to a tractor. A leveling body 4 is provided on the machine body 2 rotatably in the vertical direction ...more ...less
11
JP2018037692A
Publication/Patent Number: JP2018037692A
Publication date: 2018-03-08
Application number: 2017235072
Filing date: 2017-12-07
Abstract: PROBLEM TO BE SOLVED: To suppress deterioration in performance of a semiconductor device.SOLUTION: When a width of an active region ACT1 where a field-effect transistor Q1 is formed is smaller than that of an active region ACT2 where a field-effect transistor Q2 is formed, a surface height of an upraised source layer EP(S1) of the field-effect transistor Q1 is higher than that of an upraised source layer EP(S2) of the field-effect transistor Q2. In addition, a surface height of an upraised drain layer EP(D1) of the field-effect transistor Q1 is higher than that of an upraised drain layer EP(D2) of the field-effect transistor Q2.SELECTED DRAWING: Figure 6 PROBLEM TO BE SOLVED: To suppress deterioration in performance of a semiconductor device.SOLUTION: When a width of an active region ACT1 where a field-effect transistor Q1 is formed is smaller than that of an active region ACT2 where a field-effect transistor Q2 is formed, a ...more ...less
12
US10121705B2
Publication/Patent Number: US10121705B2
Publication date: 2018-11-06
Application number: 14/469,920
Filing date: 2014-08-27
Abstract: To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor. To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of ...more ...less
13
US9978839B2
Publication/Patent Number: US9978839B2
Publication date: 2018-05-22
Application number: 15/628,925
Filing date: 2017-06-21
Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode. Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the ...more ...less
14
US20180219067A1
Publication/Patent Number: US20180219067A1
Publication date: 2018-08-02
Application number: 15/925,850
Filing date: 2018-03-20
Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode. Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the ...more ...less
15
JP2018042544A
Publication/Patent Number: JP2018042544A
Publication date: 2018-03-22
Application number: 2017002827
Filing date: 2017-01-11
Abstract: PROBLEM TO BE SOLVED: To provide an agricultural work machine capable of improving safety.SOLUTION: An agricultural work machine 1 includes: a tillage body 3 performing tillage work; and a ground levelling body 4 performing ground levelling work behind the tillage body 3. The agricultural work machine 1 includes ridging means 6 ridging on the tillage body 3 side. The ridging means 6 includes a riding body 42 performing ridging work. The ridging body 42 can be switched between a work state for ridging on the tillage body 3 side and a non-work state inclined to an inner side such that a work face faces an upper side.SELECTED DRAWING: Figure 1 PROBLEM TO BE SOLVED: To provide an agricultural work machine capable of improving safety.SOLUTION: An agricultural work machine 1 includes: a tillage body 3 performing tillage work; and a ground levelling body 4 performing ground levelling work behind the tillage body 3. The ...more ...less
16
TW201804537A
Publication/Patent Number: TW201804537A
Publication date: 2018-02-01
Application number: 106134079
Filing date: 2013-04-17
Abstract: The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1. The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate ...more ...less
17
US20180019260A1
Publication/Patent Number: US20180019260A1
Publication date: 2018-01-18
Application number: 15/695,410
Filing date: 2017-09-05
Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer. On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed ...more ...less
18
WO2018016171A1
Publication/Patent Number: WO2018016171A1
Publication date: 2018-01-25
Application number: 2017019209
Filing date: 2017-05-23
Abstract: A technology disclosed in the present description relates to a technology of suppressing dielectric breakdown in the off-state of a silicon carbide semiconductor device without deteriorating process throughput or yield. A silicon carbide semiconductor device relating to the technology disclosed in the present description is provided with: a first conductivity-type drift layer (2); a threading dislocation (TD) formed by penetrating the drift layer (2); and a second conductivity-type electric field mitigation region (12) A technology disclosed in the present description relates to a technology of suppressing dielectric breakdown in the off-state of a silicon carbide semiconductor device without deteriorating process throughput or yield. A silicon carbide semiconductor device relating to the ...more ...less
19
US9935125B2
Publication/Patent Number: US9935125B2
Publication date: 2018-04-03
Application number: 13/859,297
Filing date: 2013-04-09
Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer. On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed ...more ...less
20
CN107835824A
Publication/Patent Number: CN107835824A
Publication date: 2018-03-23
Application number: 201680041126
Filing date: 2016-07-08
Abstract: Provided is a fluororesin not prone to blistering or cracking even when rapidly depressurized from a high-temperature, high-pressure state. A fluororesin including vinylidene fluoride units, the fluororesin characterized in that the vinylidene fluoride units are 10.0-100 mol% of all monomer units constituting part of the fluororesin, and the weight reduction percentage of the fluororesin when heated for 2 hours at 300 DEG C is 0.1% or less. Provided is a fluororesin not prone to blistering or cracking even when rapidly depressurized from a high-temperature, high-pressure state. A fluororesin including vinylidene fluoride units, the fluororesin characterized in that the vinylidene fluoride units are 10.0-100 mol% of ...more ...less