Country
Full text data for US,EP,CN
Type
Legal Validity
Legal Status
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC(Section)
IPC(Class)
IPC(Subclass)
IPC(Group)
IPC(Subgroup)
Agent
Agency
Claims Number
Figures Number
Citation Number of Times
Assignee Number
No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1 US10593656B2
Three-dimensional package structure
Publication/Patent Number: US10593656B2 Publication Date: 2020-03-17 Application Number: 15/409,568 Filing Date: 2017-01-19 Inventor: Wen, Chau-chun   Liu, Chun-tiao   Chen, Da-jung   Assignee: CYNTEC CO., LTD   IPC: H01L25/10 Abstract: The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer. The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is ...More ...Less
2 US10568551B2
Hearing diagnosis device and hearing diagnosis method
Publication/Patent Number: US10568551B2 Publication Date: 2020-02-25 Application Number: 15/716,520 Filing Date: 2017-09-27 Inventor: Wu, Hau-tieng   Wang, Pa-chun   Liu, Yi-wen   Assignee: National Tsing Hua University   IPC: A61B5/00 Abstract: A hearing diagnosis device and a hearing diagnosis method are provided. The device includes a storage unit, an otoacoustic emission detecting module, and a hearing diagnosis management module. The storage unit stores a hearing diagnosis image sample database and a hearing information sample database. The otoacoustic emission detecting module is configured to perform an otoacoustic emission detecting operation by playing a test audio to an ear of a user to obtain a first hearing diagnosis image corresponding to the ear. The hearing diagnosis management module is configured to perform a hearing diagnosis operation according to the first hearing diagnosis image, a plurality of hearing diagnosis image samples of the hearing diagnosis image sample database, and a plurality of hearing information samples, respectively corresponding to the hearing diagnosis image samples, of the hearing information sample database, so as to determine first hearing information of the ear. A hearing diagnosis device and a hearing diagnosis method are provided. The device includes a storage unit, an otoacoustic emission detecting module, and a hearing diagnosis management module. The storage unit stores a hearing diagnosis image sample database and a hearing ...More ...Less
3 US2020066538A1
METHODS OF ENHANCING SURFACE TOPOGRAPHY ON A SUBSTRATE FOR INSPECTION
Publication/Patent Number: US2020066538A1 Publication Date: 2020-02-27 Application Number: 16/670,107 Filing Date: 2019-10-31 Inventor: Liao, Han-wen   Liu, Jun Xiu   Lin, Chun-chih   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/306 Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect. Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography ...More ...Less
4 US2020141098A1
SANITARY EQUIPMENT WITH WATER SUPPLAY SYSTEM, WATER ROUTE SYSTEM AND SINK
Publication/Patent Number: US2020141098A1 Publication Date: 2020-05-07 Application Number: 16/658,183 Filing Date: 2019-10-21 Inventor: Liu, Po-chun   Chiu, Wen-yi   Lee, Pin-hsing   Assignee: COMPAL ELECTRONICS, INC.   IPC: E03C1/048 Abstract: A sanitary equipment with a water supply system, a water route system, and a hand washing table are provided. The sanitary equipment includes a machine having a machine water outlet; a movable hand washing table pivoted on the machine and located below the machine water outlet, the movable hand washing table being capable of opening or retracting with respect to the machine; and a water route system disposed in the machine and connected to the machine water outlet to discharge potable water and non-potable water from the machine water outlet. A sanitary equipment with a water supply system, a water route system, and a hand washing table are provided. The sanitary equipment includes a machine having a machine water outlet; a movable hand washing table pivoted on the machine and located below the machine water outlet ...More ...Less
5 US2020025713A1
METHOD OF USING INTEGRATED ELECTRO-MICROFLUIDIC PROBE CARD
Publication/Patent Number: US2020025713A1 Publication Date: 2020-01-23 Application Number: 16/588,088 Filing Date: 2019-09-30 Inventor: Liu, Yi-shao   Lai, Fei-lung   Cheng, Chun-ren   Cheng, Chun-wen   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.   IPC: G01N27/414 Abstract: A method includes mounting an integrated electro-microfluidic probe card to a device area on a bio-sensor device wafer, wherein the electro-microfluidic probe card has a first major surface and a second major surface opposite the first major surface. The method further includes electrically connecting at least one electronic probe tip extending from the first major surface to a corresponding conductive area of the device area. The method further includes stamping a test fluid onto the device area. The method further includes measuring via the at least one electronic probe tip a first electrical property of one or more bio-FETs of the device area based on the test fluid. A method includes mounting an integrated electro-microfluidic probe card to a device area on a bio-sensor device wafer, wherein the electro-microfluidic probe card has a first major surface and a second major surface opposite the first major surface. The method further includes ...More ...Less
6 US10529111B1
Facial recognition method for video conference and server using the method
Publication/Patent Number: US10529111B1 Publication Date: 2020-01-07 Application Number: 16/419,607 Filing Date: 2019-05-22 Inventor: Wu, Chun-te   Shi, Zhi-gang   Liu, Dong-lin   Meng, Wen   Zhong, Yu-qiang   Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.   IPC: G06T13/20 Abstract: A facial recognition method for video conferencing requiring a reduced bandwidth and transmitting video and audio frames synchronously first determines whether a 3D body model of a first user at a local end has been currently retrieved or is otherwise retrievable from a historical database. Multiple audio frames of first user are collected and audio frequency at a specific range are filtered out. An envelope curve of the first audio frames and multiple attacking time periods and multiple releasing time periods of the envelope curve is calculated and correlated with lip movements of first user. Information packets of same and head-rotating and limb-swinging images of the first user are transmitted to a remote second user so that the 3D body model can simulate and show lip shapes and other movement of the first user. A facial recognition method for video conferencing requiring a reduced bandwidth and transmitting video and audio frames synchronously first determines whether a 3D body model of a first user at a local end has been currently retrieved or is otherwise retrievable from a ...More ...Less
7 US2020045845A1
FAN SYSTEM AND SOUND SUPPRESSION METHOD THEREOF
Publication/Patent Number: US2020045845A1 Publication Date: 2020-02-06 Application Number: 16/191,683 Filing Date: 2018-11-15 Inventor: Wang, Cheng-pang   Liu, Chih-chun   Su, Hung Jen   Wu, Wen-chen   Assignee: Winstron Corp.   IPC: H05K7/20 Abstract: A fan system is used for dissipating heat of an electronic device. The fan system includes a fan, a hollow structure, and a control circuit. Sound waves made by the fan are transmitted to an interior of the hollow structure when the fan is operating. The control circuit is connected to the hollow structure and is configured to control deformation/deformations of the hollow structure according to a state/states of the fan and/or the electronic device, which change a volume of the interior of the hollow structure for making a resonance frequency of the hollow structure being approximate to a rotation speed of the fan or being the same as the rotation speed of the fan. A fan system is used for dissipating heat of an electronic device. The fan system includes a fan, a hollow structure, and a control circuit. Sound waves made by the fan are transmitted to an interior of the hollow structure when the fan is operating. The control circuit is ...More ...Less
8 US2020165859A1
SPACE ADJUSTMENT SYSTEM AND CONTROL METHOD THEREOF
Publication/Patent Number: US2020165859A1 Publication Date: 2020-05-28 Application Number: 16/286,625 Filing Date: 2019-02-27 Inventor: Hong, Ruei-hong   Chiu, Wen-yi   Wang, Wei-jun   Liu, Po-chun   Assignee: COMPAL ELECTRONICS, INC.   IPC: E05F15/73 Abstract: A space adjustment system and a control method thereof are provided. The space adjustment system includes a body, at least one door leaf, at least one motor, and a control circuit. The door leaf is movably disposed at the body. The door panel of each door leaf includes a panel. The motor can drive the motion of the door leaf. The control circuit is coupled with the panel of the door leaf and motor. The control circuit controls the motor to drive the door leaf, and adjusts the transparency or display function of the panel on the corresponding door leaf in response to a location of the door leaf. Accordingly, multiple space type can be created. A space adjustment system and a control method thereof are provided. The space adjustment system includes a body, at least one door leaf, at least one motor, and a control circuit. The door leaf is movably disposed at the body. The door panel of each door leaf includes a panel ...More ...Less
9 US2020098883A1
Metal Gate Scheme for Device and Methods of Forming
Publication/Patent Number: US2020098883A1 Publication Date: 2020-03-26 Application Number: 16/692,053 Filing Date: 2019-11-22 Inventor: Jangjian, Shiu-ko   Liu, Chi-wen   Wu, Chih-nan   Lin, Chun Che   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/49 Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment. Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over ...More ...Less
10 US2020090938A1
Metal Gate Stack Having TaAlCN Layer
Publication/Patent Number: US2020090938A1 Publication Date: 2020-03-19 Application Number: 16/685,800 Filing Date: 2019-11-15 Inventor: Jangjian, Shiu-ko   Wang, Ting-chun   Jeng, Chi-cherng   Liu, Chi-wen   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/28 Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%. Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric ...More ...Less
11 US2020083168A1
Dielectric Film for Semiconductor Fabrication
Publication/Patent Number: US2020083168A1 Publication Date: 2020-03-12 Application Number: 16/681,556 Filing Date: 2019-11-12 Inventor: Wu, Cheng-yi   Chu, Li-hsuan   Wen, Ching-wen   Hung, Chia-chun   Chang, Chen Liang   Lee, Chin-szu   Liu, Hsiang   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/532 Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal. A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the ...More ...Less
12 US10658296B2
Dielectric film for semiconductor fabrication
Publication/Patent Number: US10658296B2 Publication Date: 2020-05-19 Application Number: 15/282,258 Filing Date: 2016-09-30 Inventor: Wu, Cheng-yi   Chu, Li-hsuan   Wen, Ching-wen   Hung, Chia-chun   Chang, Chen Liang   Lee, Chin-szu   Liu, Hsiang   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L21/00 Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal. A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the ...More ...Less
13 US2020016635A1
PHOTORESIST REMOVAL METHOD USING RESIDUE GAS ANALYZER
Publication/Patent Number: US2020016635A1 Publication Date: 2020-01-16 Application Number: 16/503,571 Filing Date: 2019-07-04 Inventor: Hsiao, Chun-jen   Chen, Ya-ping   Lin, Chien-hung   Liu, Wen-pin   Chen, Chin-wen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: B08B7/00 Abstract: A photoresist removal method is provided. The photoresist removal method includes analyzing the process status of each of a number of semiconductor substrate models undergoing a tested plasma ash process by a residue gas analyzer. The tested plasma ash processes for the semiconductor substrate models utilize a plurality of tested recipes. The photoresist removal method further includes selecting one of the tested recipes as a process recipe based on the analysis results from the residue gas analyzer and at least one expected performance criterion. In addition, the photoresist removal method includes performing a plasma ash process on a semiconductor substrate according to the process recipe to remove a photoresist layer from the semiconductor substrate. A photoresist removal method is provided. The photoresist removal method includes analyzing the process status of each of a number of semiconductor substrate models undergoing a tested plasma ash process by a residue gas analyzer. The tested plasma ash processes for the ...More ...Less
14 US2020150080A1
CMOS COMPATIBLE BIOFET
Publication/Patent Number: US2020150080A1 Publication Date: 2020-05-14 Application Number: 16/727,738 Filing Date: 2019-12-26 Inventor: Kalnitsky, Alexander   Liu, Yi-shao   Liang, Kai-chih   Chu, Chia-hua   Cheng, Chun-ren   Cheng, Chun-wen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01N27/414 Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity. The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The ...More ...Less