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1
US10256180B2
Publication/Patent Number: US10256180B2
Publication date: 2019-04-09
Application number: 15/461,499
Filing date: 2017-03-17
Abstract: A package structure includes a substrate, an insulator, a plurality of pads and a patterned circuit layer. The substrate includes a plurality of through holes. The insulator covers the substrate and is filled in the through hole. The conductive vias are located in the through holes and penetrate the insulator filled in the through holes. The pads are disposed on an upper surface and a lower surface of the insulator and electrically connected to the conductive vias. A bottom surface of each pad is lower than the top surface of the insulator. The patterned circuit layer is disposed on the top surface of the insulator and connected to the conductive vias and the pads. A bottom surface of the patterned circuit layer is lower than the top surface of the insulator. A package structure includes a substrate, an insulator, a plurality of pads and a patterned circuit layer. The substrate includes a plurality of through holes. The insulator covers the substrate and is filled in the through hole. The conductive vias are located in the through ...more ...less
2
EP3479882A1
Publication/Patent Number: EP3479882A1
Publication date: 2019-05-08
Application number: 18176565.2
Filing date: 2018-06-07
Abstract: A display device (100) including a status display module (130), a microcontroller (120) and a communication module is provided. The status display module (130) includes a plurality of status indicator lights. The status display module (130) is configured to receive a control signal to determine a bright/dark state of each of the status indicator lights. The microcontroller (120) is configured to provide the control signal to the status display module (130). The microcontroller (120) communicates with an external computer device through the communication module. When the external computer device executes a specific application program, the microcontroller (120) receives a setting parameter provided by the specific application program through the communication module, and the microcontroller (120) generates and provides the control signal to the status display module (130) based on the setting parameter to control the bright/dark state of each of the status indicator lights. A display device (100) including a status display module (130), a microcontroller (120) and a communication module is provided. The status display module (130) includes a plurality of status indicator lights. The status display module (130) is configured to receive a control ...more ...less
3
US10324349B2
Publication/Patent Number: US10324349B2
Publication date: 2019-06-18
Application number: 15/181,425
Filing date: 2016-06-14
Abstract: A reflectance-adjustable reflector including a phase modulation element and a first polarizer is provided. The phase modulation element includes a first substrate, a second substrate opposite to the first substrate, a phase modulation layer located between the first substrate and the second substrate, a first electrode layer located between the first substrate and the phase modulation layer, and a second electrode layer located between the second substrate and the phase modulation layer. Thicknesses of the first substrate and the second substrate are between 0.01 mm and 0.5 mm. The first polarizer is disposed on the first substrate. The first substrate is located between the first polarizer and the first electrode layer. A total thickness of the phase modulation element and the first polarizer is less than 1 mm. A reflectance-adjustable display device is also provided. A reflectance-adjustable reflector including a phase modulation element and a first polarizer is provided. The phase modulation element includes a first substrate, a second substrate opposite to the first substrate, a phase modulation layer located between the first substrate ...more ...less
4
US10453688B2
Publication/Patent Number: US10453688B2
Publication date: 2019-10-22
Application number: 15/253,074
Filing date: 2016-08-31
Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy including components of the first metal layer, second metal layer, and the semiconductor substrate. A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is ...more ...less
5
US2019094710A1
Publication/Patent Number: US2019094710A1
Publication date: 2019-03-28
Application number: 15/715,943
Filing date: 2017-09-26
Abstract: Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation. Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation ...more ...less
6
US10429341B2
Publication/Patent Number: US10429341B2
Publication date: 2019-10-01
Application number: 15/350,399
Filing date: 2016-11-14
Abstract: A method for testing a partially fabricated bio-sensor device wafer includes aligning the partially fabricated bio-sensor device wafer on a wafer stage of a wafer-level bio-sensor processing tool. The method further includes mounting an integrated electro-microfluidic probe card to a device area on the partially fabricated bio-sensor device wafer, wherein the electro-microfluidic probe card has a first major surface. The method further includes electrically connecting one or more electronic probe tips disposed on the first major surface of the integrated electro-microfluidic probe card to conductive areas of the device area. The method further includes flowing a test fluid from a fluid supply to the integrated electro-microfluidic probe card. The method further includes electrically measuring via the one or more electronic probe tips a first electrical property of one or more bio-FETs of the device area based on the test fluid flow. A method for testing a partially fabricated bio-sensor device wafer includes aligning the partially fabricated bio-sensor device wafer on a wafer stage of a wafer-level bio-sensor processing tool. The method further includes mounting an integrated electro-microfluidic probe card ...more ...less
7
US2019147134A1
Publication/Patent Number: US2019147134A1
Publication date: 2019-05-16
Application number: 15/812,826
Filing date: 2017-11-14
Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features. Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying ...more ...less
8
US10346286B2
Publication/Patent Number: US10346286B2
Publication date: 2019-07-09
Application number: 15/902,161
Filing date: 2018-02-22
Abstract: According to one embodiment, a method, computer system, and computer program product for memory corruption diagnosis is provided. The present invention may include generating a pattern expression (PE) header file, wherein a plurality of common datatypes associated with a software program are pre-defined. The invention may further include generating a PE for each of the plurality of common datatypes, and generating a PE table by merging the generated PEs for each of the plurality of common datatypes. Upon discovery that memory corruption has occurred, the invention may include transmitting a recorded state of the software program as a core dump file to a server, and using a dump utility to identify overlay content of the core dump file. Lastly, the invention may include identifying a possible source program of the memory corruption by matching the PE tables against the illegally-written overlay content. According to one embodiment, a method, computer system, and computer program product for memory corruption diagnosis is provided. The present invention may include generating a pattern expression (PE) header file, wherein a plurality of common datatypes associated with a ...more ...less
9
US10387638B2
Publication/Patent Number: US10387638B2
Publication date: 2019-08-20
Application number: 15/444,489
Filing date: 2017-02-28
Abstract: A system, method, and computer product for managing a password includes receiving a new password set by a user via a key input interface, generating a diagram based on key positions, on the key input interface, of a plurality of characters associated with said new password, storing a diagram into a memory device coupled to the processing device, and providing said diagram stored in the memory device to the user as a password hint. A system, method, and computer product for managing a password includes receiving a new password set by a user via a key input interface, generating a diagram based on key positions, on the key input interface, of a plurality of characters associated with said new password ...more ...less
10
US2019042685A1
Publication/Patent Number: US2019042685A1
Publication date: 2019-02-07
Application number: 16/133,110
Filing date: 2018-09-17
Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges. Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected ...more ...less
11
USD847958S1
Publication/Patent Number: USD847958S1
Publication date: 2019-05-07
Application number: 29/634,803
Filing date: 2018-01-25
IPC:
12
US10384933B2
Publication/Patent Number: US10384933B2
Publication date: 2019-08-20
Application number: 15/643,536
Filing date: 2017-07-07
Abstract: A method of making a micro electromechanical system (MEMS) package includes patterning a substrate to form a MEMS section. The method further includes bonding a carrier to a surface of the substrate. The carrier is free of active devices. The carrier includes a carrier bond pad on a surface of the carrier opposite the MEMS section. The carrier bond pad is electrically connected to the MEMS section. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad. The bonding of the wafer bond pad to the carrier bond pad includes re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad. A method of making a micro electromechanical system (MEMS) package includes patterning a substrate to form a MEMS section. The method further includes bonding a carrier to a surface of the substrate. The carrier is free of active devices. The carrier includes a carrier bond pad ...more ...less
13
US2019148555A1
Publication/Patent Number: US2019148555A1
Publication date: 2019-05-16
Application number: 16/230,245
Filing date: 2018-12-21
Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric. FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface ...more ...less