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1
US9905638B1
Publication/Patent Number: US9905638B1
Publication date: 2018-02-27
Application number: 15/281,865
Filing date: 2016-09-30
Abstract: A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant on an inner surface of the high aspect ratio, substantially perpendicular trench, the first cycle comprising alternately depositing silicon at a first constant pressure and etching the deposited silicon at an etching pressure that ramps up from a first value to a second value, the second dopant having a second conductivity type that is opposite from the first conductivity type. A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant ...more ...less
2
CN107887271A
Publication/Patent Number: CN107887271A
Publication date: 2018-04-06
Application number: 201710913013
Filing date: 2017-09-30
Abstract: The invention relates to silicon epitaxy for high aspect ratio, substantially perpendicular deep silicon trench. A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant on an inner surface of the high aspect ratio, substantially perpendicular trench, the first cycle comprising alternately depositing silicon at a first constant pressure and etching the deposited silicon at anetching pressure that ramps up from a first value to a second value, the second dopant having a second conductivity type that is opposite from the first conductivity type. The invention relates to silicon epitaxy for high aspect ratio, substantially perpendicular deep silicon trench. A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first ...more ...less
3
KR20160003225A
Publication/Patent Number: KR20160003225A
Publication date: 2016-01-08
Application number: 20157034173
Filing date: 2014-05-29
Abstract: 채널부에 SiGe 또는 Ge막을 사용한 반도체 장치의 제조 방법
4
US20160126337A1
Publication/Patent Number: US20160126337A1
Publication date: 2016-05-05
Application number: 14/894,620
Filing date: 2014-05-29
Abstract: A substrate processing apparatus includes a substrate having an SiGe film or Ge film exposed on at least a portion of a surface thereof, a process chamber configured to process the substrate, an etching gas supply part configured to supply an etching gas into the process chamber, a deposition gas supply part configured to supply gas containing at least an Si-containing gas as a deposition gas into the process chamber, and a control part configured to control the deposition gas supply part and the etching gas supply part so as to remove a Ge oxide film formed on a surface of the SiGe film or the Ge film by supplying the etching gas and to epitaxially grow an Si-containing film on at least the SiGe film or the Ge film by supplying the Si-containing gas after removing the Ge oxide film by the supply of the etching gas. A substrate processing apparatus includes a substrate having an SiGe film or Ge film exposed on at least a portion of a surface thereof, a process chamber configured to process the substrate, an etching gas supply part configured to supply an etching gas into the process ...more ...less
5
JP2015173212A
Publication/Patent Number: JP2015173212A
Publication date: 2015-10-01
Application number: 2014049012
Filing date: 2014-03-12
Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a device capable of removing a natural oxide film generated on a surface of a material such as SiGe or Ge used in a channel unit.SOLUTION: A substrate processing device comprises: a substrate having a silicon germanium film or a germanium film on the surface thereof; a processing chamber for processing the substrate; a germanium-containing gas supply unit which is provided in the processing chamber and supplies at least a germanium-containing gas into the processing chamber; an etching gas supply unit which is provided in the processing chamber and supplies an etching gas into the processing chamber; and a control unit which controls the germanium-containing gas supply unit to form a silicon germanium film containing oxygen or a germanium oxide film on the germanium film by supplying the germanium-containing gas and the etching gas supply unit to remove the germanium oxide film by supplying the etching gas. PROBLEM TO BE SOLVED: To provide a method for manufacturing a device capable of removing a natural oxide film generated on a surface of a material such as SiGe or Ge used in a channel unit.SOLUTION: A substrate processing device comprises: a substrate having a silicon germanium ...more ...less
6
TWI497610B
Publication/Patent Number: TWI497610B
Publication date: 2015-08-21
Application number: 102120506
Filing date: 2013-06-10
Abstract: A method for processing a substrate having an insulating film in at least a portion of a surface thereof
7
TW201522697A
Publication/Patent Number: TW201522697A
Publication date: 2015-06-16
Application number: 103119029
Filing date: 2014-05-30
Abstract: Provided are a method for manufacturing a semiconductor device wherein an SiGe or Ge film is used for a channel section
8
JP5643635B2
Publication/Patent Number: JP5643635B2
Publication date: 2014-12-17
Application number: 2010287374
Filing date: 2010-12-24
Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which the operating speed of a bipolar transistor can be accelerated.SOLUTION: A semiconductor device comprises an n-type collector layer 20 provided above a single crystal Si substrate 1
9
JP5547516B2
Publication/Patent Number: JP5547516B2
Publication date: 2014-07-16
Application number: 2010033543
Filing date: 2010-02-18
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device reduced in the area of a bipolar transistor while junction leakage due to crystal defects is prevented
10
TW201405669A
Publication/Patent Number: TW201405669A
Publication date: 2014-02-01
Application number: 102120506
Filing date: 2013-06-10
Abstract: A method for processing a substrate having an insulating film in at least a portion of a surface thereof
11
WO2014192870A1
Publication/Patent Number: WO2014192870A1
Publication date: 2014-12-04
Application number: 2014064262
Filing date: 2014-05-29
Abstract: Provided are a method for manufacturing a semiconductor device wherein an SiGe or Ge film is used for a channel section
12
KR101455251B1
Publication/Patent Number: KR101455251B1
Publication date: 2014-10-27
Application number: 20130060848
Filing date: 2013-05-29
Abstract: The present invention provides a method for manufacturing a semiconductor device
13
JP2014165293A
Publication/Patent Number: JP2014165293A
Publication date: 2014-09-08
Application number: 2013034122
Filing date: 2013-02-25
Assignee: HITACHI LTD
Abstract: PROBLEM TO BE SOLVED: To improve the reduction phenomenon of breakdown voltage and the NBTI deterioration phenomenon at a gate voltage high slew rate
14
US8415762B2
Publication/Patent Number: US8415762B2
Publication date: 2013-04-09
Application number: 11/933,195
Filing date: 2007-10-31
Assignee: Hitachi, Ltd.
Abstract: The external base electrode has a two-layered structure where a p-type polysilicon film doped with a medium concentration of boron is laminated on a p-type polysilicon film doped with a high concentration of boron. Therefore, since the p-type polysilicon film doped with a high concentration of boron is in contact with an intrinsic base layer at a junction portion between the external base electrode and the intrinsic base layer, the resistance of the junction portion can be reduced. In addition, since the resistance of the external base electrode becomes a parallel resistance of the two layers of the p-type polysilicon films, the resistance of the p-type polysilicon film whose boron concentration is relatively lower is dominant. The external base electrode has a two-layered structure where a p-type polysilicon film doped with a medium concentration of boron is laminated on a p-type polysilicon film doped with a high concentration of boron. Therefore, since the p-type polysilicon film doped with a high ...more ...less
15
KR20130138674A
Publication/Patent Number: KR20130138674A
Publication date: 2013-12-19
Application number: 20130060848
Filing date: 2013-05-29
Abstract: The present invention provides a method for manufacturing a semiconductor device
16
JP2013258188A
Publication/Patent Number: JP2013258188A
Publication date: 2013-12-26
Application number: 2012131857
Filing date: 2012-06-11
Abstract: PROBLEM TO BE SOLVED: To provide a method for processing a substrate capable of forming a source/drain region having desired dopant concentration while securing a deposition speed
17
US20130344689A1
Publication/Patent Number: US20130344689A1
Publication date: 2013-12-26
Application number: 13/915,054
Filing date: 2013-06-11
Abstract: A method for processing a substrate having an insulating film in at least a portion of a surface thereof, a source portion, a drain portion, and a gate portion thereon, and a monocrystalline silicon-based structure in a gate channel disposed under the gate portion. The method for processing a substrate includes: growing amorphous doped silicon and monocrystalline doped silicon by supplying at least silicon-containing gas and doping gas; and monocrystallizing the amorphous doped silicon by using the monocrystalline doped silicon as a seed by heating the amorphous doped silicon and the monocrystalline doped silicon. A method for processing a substrate having an insulating film in at least a portion of a surface thereof, a source portion, a drain portion, and a gate portion thereon, and a monocrystalline silicon-based structure in a gate channel disposed under the gate portion. The method ...more ...less
18
JP2012134423A
Publication/Patent Number: JP2012134423A
Publication date: 2012-07-12
Application number: 2010287374
Filing date: 2010-12-24
Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which the operating speed of a bipolar transistor can be accelerated.SOLUTION: A semiconductor device comprises an n-type collector layer 20 provided above a single crystal Si substrate 1
19
JP2012124416A
Publication/Patent Number: JP2012124416A
Publication date: 2012-06-28
Application number: 2010275807
Filing date: 2010-12-10
Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of forming a trench isolation using a formation step of a MOS transistor.SOLUTION: A manufacturing method of a semiconductor device having a DTI layer 20 and a MOS transistor on a silicon substrate 1 forms a deep trench on the silicon substrate 1 PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of forming a trench isolation using a formation step of a MOS transistor.SOLUTION: A manufacturing method of a semiconductor device having a DTI layer 20 and a MOS transistor on a silicon ...more ...less
20
JP5085092B2
Publication/Patent Number: JP5085092B2
Publication date: 2012-11-28
Application number: 2006296499
Filing date: 2006-10-31
Assignee: HITACHI LTD
Abstract: PROBLEM TO BE SOLVED: To provide a hetero-junction bipolar transistor (HBT) having a base leading-out electrode constituted with a boron-doped polycrystalline silicon film in which the base resistance thereof is reduced. SOLUTION: This base leading-out electrode 13 has a bilayer structure in which a p-type polycrystalline silicon film 13b in which boron is doped in a medium concentration is laminated on a p-type polycrystalline silicon film 13a in which boron is doped in a high concentration. Accordingly PROBLEM TO BE SOLVED: To provide a hetero-junction bipolar transistor (HBT) having a base leading-out electrode constituted with a boron-doped polycrystalline silicon film in which the base resistance thereof is reduced. SOLUTION: This base leading-out electrode 13 has a bilayer ...more ...less