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1
US2018047855A1
Publication/Patent Number: US2018047855A1
Publication date: 2018-02-15
Application number: 20/151,555
Filing date: 2015-05-15
Assignee: Hitachi, Ltd.
Abstract: In a Schottky barrier diode comprising silicon carbide: an active region includes a first semiconductor region of a first conductivity type configuring a first Schottky junction having a plurality of linear patterns between a first electrode and the first semiconductor region and a second semiconductor region of a second conductivity type adjacent to the first Schottky junction and connected to the first electrode; at the border of the active region and a periphery region, a second Schottky junction comprising the first electrode and the first semiconductor region and having at least one annular pattern surrounding the linear patterns is provided and the second semiconductor region is adjacent to the second Schottky junction and is connected to the first electrode; and the first and second Schottky junctions are conductive parts and the second semiconductor region is a nonconductive part in a forward bias state. In a Schottky barrier diode comprising silicon carbide: an active region includes a first semiconductor region of a first conductivity type configuring a first Schottky junction having a plurality of linear patterns between a first electrode and the first semiconductor region ...more ...less
2
US9941430B2
Publication/Patent Number: US9941430B2
Publication date: 2018-04-10
Application number: 15/442,113
Filing date: 2017-02-24
Assignee: HITACHI, LTD.
Abstract: A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers. A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or ...more ...less
3
JP6203915B2
Publication/Patent Number: JP6203915B2
Publication date: 2017-09-27
Application number: 2016139253
Filing date: 2016-07-14
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has a thin film BOX-SOI structure and which can support a high-speed operation of a logic circuit and a stable operation of a memory circuit at the same time.SOLUTION: A semiconductor device having a first field effect transistor comprises: an insulation film 4 formed on a semiconductor support substrate 1; a semiconductor layer 3 formed on the insulation film 4; a first gate electrode 20 formed on the semiconductor layer 3; a first source region 8 and a first drain region 9 which are formed in the semiconductor layer 3 and have a second conductivity type opposite to the first conductivity type; a second conductivity type first impurity region 6W formed on the semiconductor support substrate 1; and a first conductivity type second impurity region 6Za formed in the first impurity region 6W. The second impurity region 6Za is electrically isolated from the semiconductor support substrate 1 by the first impurity region 6W. In the second impurity region 6Za PROBLEM TO BE SOLVED: To provide a semiconductor device which has a thin film BOX-SOI structure and which can support a high-speed operation of a logic circuit and a stable operation of a memory circuit at the same time.SOLUTION: A semiconductor device having a first field ...more ...less
4
JP2017212468A
Publication/Patent Number: JP2017212468A
Publication date: 2017-11-30
Application number: 2017165517
Filing date: 2017-08-30
Abstract: 【課題】薄膜BOX−SOI構造であり、ロジック回路の高速動作とメモリ回路の安定動作とを両立できる半導体装置を提供する。【解決手段】半導体層3は、第1導電型の半導体支持基板1上の絶縁膜4上に形成されている。半導体支持基板1には、第2導電型の第1不純物領域6Wと、第1導電型の第2不純物領域6Zaと、第1導電型の第3不純物領域25とが形成されている。第2不純物領域6Zaは第1不純物領域6Wによって半導体支持基板1と分離されている。半導体支持基板1の第1領域には、半導体層3および絶縁膜4が除去された第1給電部d1が設けられている。第3不純物領域25は、第1領域に形成された第1素子分離膜2の底よりも浅い位置に形成されている。第2不純物領域6Zaは、第1領域に形成された第1素子分離膜2の底を囲むように形成され、かつ、第1給電部d1を介して第1のバックバイアスV1が印加される領域である。【選択図】図5 【課題】薄膜BOX−SOI構造であり、ロジック回路の高速動作とメモリ回路の安定動作とを両立できる半導体装置を提供する。【解決手段】半導体層3は、第1導電型の半導体支持基板1上の絶縁膜4上に形成されている。半導体支持基板1には、第2導電型の第1不純物領域6Wと、第1導電型の第2不純物領域6Zaと、第1導電型の第3不純物領域25とが形成されている。第2不純物領域6Zaは第1不純物領域6Wによって半導体支持基板1と分離されている。半導体支持基板1の第1領域には、半導体層3および絶縁膜4が除去された第1給電部d1が設けられている。第3不純物領域25は、第1領域に ...more ...less
5
US9799734B2
Publication/Patent Number: US9799734B2
Publication date: 2017-10-24
Application number: 14/899,032
Filing date: 2013-06-17
Assignee: Hitachi, Ltd.
Abstract: Provided is a vertical MOSFET in which a conduction deterioration phenomenon is prevented during a current return operation and an on-voltage is low during the current return operation. A semiconductor device includes a hole barrier region that is provided between a second-conductivity-type body region and a first-conductivity-type epitaxial layer below a second-conductivity-type body contact region and functions as a potential barrier to a hole which flows from a source electrode to the first-conductivity-type epitaxial layer through the second-conductivity-type body contact region and the second-conductivity-type body region. Provided is a vertical MOSFET in which a conduction deterioration phenomenon is prevented during a current return operation and an on-voltage is low during the current return operation. A semiconductor device includes a hole barrier region that is provided between a ...more ...less
6
US20170288076A1
Publication/Patent Number: US20170288076A1
Publication date: 2017-10-05
Application number: 15/442,113
Filing date: 2017-02-24
Assignee: HITACHI, LTD.
Abstract: A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers. A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or ...more ...less
7
EP3225587A1
Publication/Patent Number: EP3225587A1
Publication date: 2017-10-04
Application number: 16163414.2
Filing date: 2016-03-31
Assignee: Hitachi, Ltd.
Abstract: A silicon-based quantum dot device is (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate. The device is configured to provide at least one quantum dot (5_1 and 5_2) in the silicon or silicon-germanium layer (7). In order to increase the intervalley splitting in the quantum dots the layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eigth or five monolayers. The device further comprises laterally placed gates (8), as well as two single-electron tranistsors (3) at respective sides of the quantum dots. A silicon-based quantum dot device is (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate. The device is configured to provide at least one quantum dot (5_1 and 5_2) in the silicon or silicon-germanium ...more ...less
8
US9825166B2
Publication/Patent Number: US9825166B2
Publication date: 2017-11-21
Application number: 14/760,166
Filing date: 2013-01-23
Assignee: HITACHI, LTD.
Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability. Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the ...more ...less
9
US20160133706A1
Publication/Patent Number: US20160133706A1
Publication date: 2016-05-12
Application number: 14/899,032
Filing date: 2013-06-17
Assignee: HITACHI, LTD.
Abstract: Provided is a vertical MOSFET in which a conduction deterioration phenomenon is prevented during a current return operation and an on-voltage is low during the current return operation. A semiconductor device includes a hole barrier region that is provided between a second-conductivity-type body region and a first-conductivity-type epitaxial layer below a second-conductivity-type body contact region and functions as a potential barrier to a hole which flows from a source electrode to the first-conductivity-type epitaxial layer through the second-conductivity-type body contact region and the second-conductivity-type body region. Provided is a vertical MOSFET in which a conduction deterioration phenomenon is prevented during a current return operation and an on-voltage is low during the current return operation. A semiconductor device includes a hole barrier region that is provided between a ...more ...less
10
DE112013007095T5
Publication/Patent Number: DE112013007095T5
Publication date: 2016-02-25
Application number: 112013007095
Filing date: 2013-06-17
Assignee: Hitachi, Ltd.
Abstract: Es wird ein vertikaler MOSFET geschaffen
11
JP6029330B2
Publication/Patent Number: JP6029330B2
Publication date: 2016-11-24
Application number: 2012127131
Filing date: 2012-06-04
Assignee: HITACHI LTD
Abstract: PROBLEM TO BE SOLVED: To provide a technique capable of improving performance of a semiconductor device.SOLUTION: A vertical MISFET50 comprises an ntype SiC substrate 10 in which a drain electrode 11 is formed on a lower surface thereof and an ntype epitaxial layer 12 is formed on an upper surface thereof. A P type body region 13 is formed in an upper layer part of the ntype epitaxial layer 12 PROBLEM TO BE SOLVED: To provide a technique capable of improving performance of a semiconductor device.SOLUTION: A vertical MISFET50 comprises an ntype SiC substrate 10 in which a drain electrode 11 is formed on a lower surface thereof and an ntype epitaxial layer 12 is formed ...more ...less
12
US9287292B2
Publication/Patent Number: US9287292B2
Publication date: 2016-03-15
Application number: 27/783,308
Filing date: 2008-11-25
Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support ...more ...less
13
JP2016184766A
Publication/Patent Number: JP2016184766A
Publication date: 2016-10-20
Application number: 2016139253
Filing date: 2016-07-14
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has a thin film BOX-SOI structure and which can support a high-speed operation of a logic circuit and a stable operation of a memory circuit at the same time.SOLUTION: A semiconductor device having a first field effect transistor comprises: an insulation film 4 formed on a semiconductor support substrate 1; a semiconductor layer 3 formed on the insulation film 4; a first gate electrode 20 formed on the semiconductor layer 3; a first source region 8 and a first drain region 9 which are formed in the semiconductor layer 3 and have a second conductivity type opposite to the first conductivity type; a second conductivity type first impurity region 6W formed on the semiconductor support substrate 1; and a first conductivity type second impurity region 6Za formed in the first impurity region 6W. The second impurity region 6Za is electrically isolated from the semiconductor support substrate 1 by the first impurity region 6W. In the second impurity region 6Za PROBLEM TO BE SOLVED: To provide a semiconductor device which has a thin film BOX-SOI structure and which can support a high-speed operation of a logic circuit and a stable operation of a memory circuit at the same time.SOLUTION: A semiconductor device having a first field ...more ...less
14
US20160372486A1
Publication/Patent Number: US20160372486A1
Publication date: 2016-12-22
Application number: 15/251,238
Filing date: 2016-08-30
Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other. To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support ...more ...less
15
US20160156350A1
Publication/Patent Number: US20160156350A1
Publication date: 2016-06-02
Application number: 15/018,533
Filing date: 2016-02-08
Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other. To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support ...more ...less
16
JP2016117653A
Publication/Patent Number: JP2016117653A
Publication date: 2016-06-30
Application number: 2014256290
Filing date: 2014-12-18
Assignee: KAO CORP
Abstract: PROBLEM TO BE SOLVED: To provide a powder cosmetic by which the bright and translucent skin can be finished while suppressing a powdery feel.SOLUTION: The invention provides a powder cosmetic containing the following components (A)
17
JP6039993B2
Publication/Patent Number: JP6039993B2
Publication date: 2016-12-07
Application number: 2012230755
Filing date: 2012-10-18
Assignee: KAO CORP
Abstract: PROBLEM TO BE SOLVED: To provide a powder cosmetic achieving: suppression of irregular coating after application; prevention of whitish appearance; transparent feeling; bright finishing; and inconspicuous pores.SOLUTION: A powder cosmetic contains the following components (A) and (B): (A) 50 to 90 mass% of a spherical powder having a particle diameter of 1 to 50 μm and (B) 5 to 35 mass% of a tabular powder having an average particle diameter of 5 to 30 μm and an aspect ratio of 30 to 100 PROBLEM TO BE SOLVED: To provide a powder cosmetic achieving: suppression of irregular coating after application; prevention of whitish appearance; transparent feeling; bright finishing; and inconspicuous pores.SOLUTION: A powder cosmetic contains the following components (A) ...more ...less
18
JP5875334B2
Publication/Patent Number: JP5875334B2
Publication date: 2016-03-02
Application number: 2011248059
Filing date: 2011-11-11
Assignee: HITACHI LTD
Abstract: PROBLEM TO BE SOLVED: To provide a technique capable of improving channel mobility and carrier injection speed without reducing a threshold voltage in a silicon carbide semiconductor device.SOLUTION: A position of a surface of an epitaxial layer 102 on which source regions 110 are formed is set to be lower than the interface between a gate insulating film 116 and the epitaxial layer 102. Moreover PROBLEM TO BE SOLVED: To provide a technique capable of improving channel mobility and carrier injection speed without reducing a threshold voltage in a silicon carbide semiconductor device.SOLUTION: A position of a surface of an epitaxial layer 102 on which source regions 110 ...more ...less
19
JP5925558B2
Publication/Patent Number: JP5925558B2
Publication date: 2016-05-25
Application number: 2012082196
Filing date: 2012-03-30
Assignee: KAO CORP
Abstract: PROBLEM TO BE SOLVED: To provide a solid powder cosmetic having excellent molding property and shock resistance
20
US9263571B2
Publication/Patent Number: US9263571B2
Publication date: 2016-02-16
Application number: 14/651,555
Filing date: 2012-12-28
Assignee: Hitachi, Ltd.
Abstract: When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time. When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body ...more ...less