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1
US10305462B1
Publication/Patent Number: US10305462B1
Publication date: 2019-05-28
Application number: 15/921,682
Filing date: 2018-03-15
Abstract: A high speed internal hysteresis comparator is provided. Impedance supply units are disposed at control terminals of transistors of an active load of a differential amplifier of the high-speed hysteresis comparator, such that a gain when the transistors operate in an active region and a responding speed of the high-speed hysteresis comparator are increased. A high speed internal hysteresis comparator is provided. Impedance supply units are disposed at control terminals of transistors of an active load of a differential amplifier of the high-speed hysteresis comparator, such that a gain when the transistors operate in an active ...more ...less
2
EP3282739B1
Publication/Patent Number: EP3282739B1
Publication date: 2019-03-06
Application number: 17179974.5
Filing date: 2017-07-06
Assignee: MediaTek Inc.
3
US10337689B2
Publication/Patent Number: US10337689B2
Publication date: 2019-07-02
Application number: 15/892,010
Filing date: 2018-02-08
Abstract: The present invention provides a light emitting apparatus and a lighting module, comprising: a circuit substrate, a plurality of optical sources and an optical element; the optical element comprises a translucent element and an interference element; the plurality of light sources are arranged on the circuit substrate for lighting the optical element; the optical element is arranged above the plurality of light sources; and the interference element is arranged on the translucent element, which is used to make light emitted from each of the light sources offset interference in a first polarization direction, enhance interference in a second polarization direction, and emit through the translucent element. The light emitting apparatus and the lighting module of the present invention are employed to provide a more diversified optical pattern to the user and improve the user experience. The present invention provides a light emitting apparatus and a lighting module, comprising: a circuit substrate, a plurality of optical sources and an optical element; the optical element comprises a translucent element and an interference element; the plurality of light ...more ...less
4
US10269731B2
Publication/Patent Number: US10269731B2
Publication date: 2019-04-23
Application number: 14/611,951
Filing date: 2015-02-02
Abstract: Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed. Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a ...more ...less
5
US10276542B2
Publication/Patent Number: US10276542B2
Publication date: 2019-04-30
Application number: 15/215,605
Filing date: 2016-07-21
Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer. A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is ...more ...less
6
US10234905B2
Publication/Patent Number: US10234905B2
Publication date: 2019-03-19
Application number: 15/563,967
Filing date: 2015-05-04
Abstract: Examples of a hinge for foldable components are described herein. In an example, the hinge can include a plurality of bracing elements, a bracing element from the plurality of bracing elements can be operably coupled to an adjacent bracing element from the plurality of bracing elements, to fold the plurality of bracing elements into an arcuate shape. Each bracing element can be supported and locked against the adjacent bracing element in the arcuate shape. The hinge can further include an end coupler at each longitudinal end of the hinge to couple the hinge to a flexible element. Examples of a hinge for foldable components are described herein. In an example, the hinge can include a plurality of bracing elements, a bracing element from the plurality of bracing elements can be operably coupled to an adjacent bracing element from the plurality of bracing ...more ...less
7
US20190089023A1
Publication/Patent Number: US20190089023A1
Publication date: 2019-03-21
Application number: 15/705,440
Filing date: 2017-09-15
Abstract: An integrated energy storage system can include a first, second, and third energy storage units and a controller. The first energy storage units can have a gravimetric energy density of greater than 180 Wh/kg and volumetric energy density greater than 450 Wh/L in an environmental temperature above 0° C., the second energy storage units can have a gravimetric power density of greater than 450 W/kg and volumetric power density greater than 1080 W/L in an environmental temperature above 0° C., and the third energy storage units can be configured to operate in an environmental temperature as low as −100° C. The controller can be programmed to receive inputs from voltage sensors, current sensors, and temperature sensors, and to allocate the current or power among the first, second, or third energy storage units depending on a power consumption from an application load and an environmental temperature. An integrated energy storage system can include a first, second, and third energy storage units and a controller. The first energy storage units can have a gravimetric energy density of greater than 180 Wh/kg and volumetric energy density greater than 450 Wh/L in an ...more ...less
8
US10268791B2
Publication/Patent Number: US10268791B2
Publication date: 2019-04-23
Application number: 14/967,061
Filing date: 2015-12-11
Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph. A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the ...more ...less
9
US20190056759A1
Publication/Patent Number: US20190056759A1
Publication date: 2019-02-21
Application number: 15/681,415
Filing date: 2017-08-20
Abstract: A joystick has a related control method to provide displayed object control function. The joystick includes a body, an image sensor and a processor. The body has a deformable bottom surface whereon a pattern is disposed. The image sensor is disposed under the body and adapted to capture a plurality of frames about the pattern. The processor is electrically connected with the image sensor and adapted to generate a displayed object control signal according to pattern variation within the plurality of frames. A joystick has a related control method to provide displayed object control function. The joystick includes a body, an image sensor and a processor. The body has a deformable bottom surface whereon a pattern is disposed. The image sensor is disposed under the body and adapted to ...more ...less
10
US10217563B2
Publication/Patent Number: US10217563B2
Publication date: 2019-02-26
Application number: 14/446,340
Filing date: 2014-07-30
Abstract: A method of manufacturing a multi-layer coil includes steps of providing a substrate; forming a seed layer on the substrate; and plating the seed layer with N coil layers by N current densities according to N threshold ranges, so as to form the multi-layer coil on the substrate, wherein an i-th current density of the N current densities is lower than an (i+1)-th current density of the N current densities. A first coil layer of the N coil layers is plated on the seed layer by a first current density of the N current densities. When an aspect ratio of an i-th coil layer of the N coil layers is within an i-th threshold range of the N threshold ranges, an (i+1)-th coil layer of the N coil layers is plated on the i-th coil layer by the (i+1)-th current density. A method of manufacturing a multi-layer coil includes steps of providing a substrate; forming a seed layer on the substrate; and plating the seed layer with N coil layers by N current densities according to N threshold ranges, so as to form the multi-layer coil on the substrate ...more ...less
11
US10224593B2
Publication/Patent Number: US10224593B2
Publication date: 2019-03-05
Application number: 15/217,146
Filing date: 2016-07-22
Abstract: A support assembly is provided and includes an adapter, a stand, and a dish backing structure. The adapter includes two side plates and an upper plate. The side plates are respectively located at the two sides of the adapter. The upper plate is connected to the side plates and has a lower location hole. The stand is connected to the adapter. The dish backing structure has a receiving portion and includes a top wall and two side walls respectively located at the both sides of the receiving portion. The top wall has an upper location hole. When the receiving portion is connected to the adapter, a portion of the top wall abuts against the upper plate, and a gap is formed between the top wall and the upper plate. In addition, the upper location hole is aligned with the lower location hole. A support assembly is provided and includes an adapter, a stand, and a dish backing structure. The adapter includes two side plates and an upper plate. The side plates are respectively located at the two sides of the adapter. The upper plate is connected to the side plates and ...more ...less
12
US10249958B2
Publication/Patent Number: US10249958B2
Publication date: 2019-04-02
Application number: 15/416,445
Filing date: 2017-01-26
Abstract: A dish antenna is provided. The dish antenna includes a dish, a bracket, a supporter and a receiver. The bracket is connected to the dish. The supporter is connected to the bracket. The receiver is connected to the supporter and corresponding to the dish. The bracket includes a base, a first wing plate, a second wing plate and a plurality of fastening portions. The base faces the dish. The bracket is affixed to the dish through the fastening portions. The first wing plate is disposed on a first side of the base. The second wing plate is disposed on a second side of the base. The first side is opposite to the second side. The first wing plate, the second wing plate and the fastening portions are integrally formed with the base. A dish antenna is provided. The dish antenna includes a dish, a bracket, a supporter and a receiver. The bracket is connected to the dish. The supporter is connected to the bracket. The receiver is connected to the supporter and corresponding to the dish. The bracket includes a ...more ...less
13
US20190088923A1
Publication/Patent Number: US20190088923A1
Publication date: 2019-03-21
Application number: 15/705,425
Filing date: 2017-09-15
Abstract: A method of producing a monolithically integrated high energy density solid-state battery device. The method can include positioning a substrate and depositing one or more stacked monolithically integrated high energy density solid-state electrochemical cells in series or in parallel configurations sequentially or individually. Each of these cells can have a first barrier layer, a cathode current collector deposited overlying the first barrier layer, a cathode overlying the electrically conductive layer, an anode, an anode current collector deposited overlying the solid state layer of negative electrode material, and a second barrier layer. The method can also include rapidly heating the one or more stacked cells to a target temperature for at least 60 minutes, and connecting and terminating the one or more stacked monolithically integrated high energy density solid-state electrochemical cells electrically in series or in parallel, to from a monolithically integrated high energy density solid-state battery device. A method of producing a monolithically integrated high energy density solid-state battery device. The method can include positioning a substrate and depositing one or more stacked monolithically integrated high energy density solid-state electrochemical cells in series or in ...more ...less
14
US20190088996A1
Publication/Patent Number: US20190088996A1
Publication date: 2019-03-21
Application number: 15/705,449
Filing date: 2017-09-15
Abstract: A multi-layered solid-state battery device can have a substrate member having a surface region and a thin film battery device layer overlying the barrier material. The thin film battery device layer can comprise a cathode current collector, a cathode device, an electrolyte, an anode device, and an anode current collector. The device can have a non-planar surface region configured from the thin film battery device and a first polymer material overlying the thin film battery device and configured to fill in a gap region of the non-planar surface region and a planarizing surface region configured from the first polymer material. A multi-layered solid-state battery device can have a substrate member having a surface region and a thin film battery device layer overlying the barrier material. The thin film battery device layer can comprise a cathode current collector, a cathode device, an electrolyte, an ...more ...less