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1
US10193576B2
Publication/Patent Number: US10193576B2
Publication date: 2019-01-29
Application number: 15/052,010
Filing date: 2016-02-24
Inventor: Eguchi, Yasuyuki  
Abstract: According to one embodiment, a memory system comprises a memory array, a first ECC control circuit, and a second ECC control circuit. The memory cell array stores data, a first parity generated in association with the data based on a first error correction code (ECC) scheme, and a second parity generated in association with the data and the first parity based on a second error correction code (ECC) scheme. The first ECC control circuit executes error correction using the first ECC scheme and the first parity during a read operation on the memory cell array. The second ECC control circuit executes error correction using the second ECC scheme and the second parity during a scrub operation on the memory cell array. The first ECC scheme and the second ECC scheme have error correction capabilities of different levels. According to one embodiment, a memory system comprises a memory array, a first ECC control circuit, and a second ECC control circuit. The memory cell array stores data, a first parity generated in association with the data based on a first error correction code (ECC) scheme, and ...more ...less
2
US10191661B1
Publication/Patent Number: US10191661B1
Publication date: 2019-01-29
Application number: 15/228,989
Filing date: 2016-08-04
Abstract: An integrated circuit device includes a first memory cell that stores data representative of configuration data when operating in a first mode, wherein the first memory cell stores data representative of user-accessible data when operating in a second mode. The integrated circuit device also includes a second memory cell that stores a value indicating whether the first memory cell is operating in the first mode or is operating in the second mode. The integrated circuit device further includes a switch coupled to the first memory cell and controlled by the second memory cell, wherein the switch provides a defined value to be read in place of the stored data of the first memory cell when the second memory cell stores the value indicating that the first memory cell is operating in the second mode. An integrated circuit device includes a first memory cell that stores data representative of configuration data when operating in a first mode, wherein the first memory cell stores data representative of user-accessible data when operating in a second mode. The integrated ...more ...less
3
US10198311B1
Publication/Patent Number: US10198311B1
Publication date: 2019-02-05
Application number: 14/789,799
Filing date: 2015-07-01
Abstract: Techniques for validating grid encoded data storage systems are described herein. Data stored is stored in a grid of shards using grid encoding techniques that store the data in a combination of data shards and derived shards. Each of the shards has at least a first index corresponding to one dimension of the grid, a second index corresponding to a second dimension of the grid, and a set of error-detection code values. Updates that alter the grid of shards cause updates to the error-detection code values and the update can be validated based on the updated error-detection code values. Techniques for validating grid encoded data storage systems are described herein. Data stored is stored in a grid of shards using grid encoding techniques that store the data in a combination of data shards and derived shards. Each of the shards has at least a first index ...more ...less
4
US10198312B2
Publication/Patent Number: US10198312B2
Publication date: 2019-02-05
Application number: 15/943,293
Filing date: 2018-04-02
Assignee: VMware, Inc.
Abstract: Systems and techniques are described for transferring data. A described technique includes receiving a request to transmit a data block from a first data storage device to a second data storage device. An attempt to read the data block from the first data storage device is made. A media error resulting from the attempt to read the data block from the first data storage device is detected. In response to detecting the media error, a new data block is generated and includes mismatched checksum data that causes a checksum mismatched error when the new data block is accessed. The new data block is transmitted for storage at the second data storage device in place of the data block. Systems and techniques are described for transferring data. A described technique includes receiving a request to transmit a data block from a first data storage device to a second data storage device. An attempt to read the data block from the first data storage device is made ...more ...less
5
US10198318B2
Publication/Patent Number: US10198318B2
Publication date: 2019-02-05
Application number: 15/509,732
Filing date: 2014-10-27
Assignee: HITACHI, LTD.
Abstract: A nonvolatile memory device includes: a nonvolatile memory including a plurality of physical blocks; and a memory controller configured to execute an internal process of migrating data between physical blocks. The memory controller is configured to select, based on an update frequency level which is identified with respect to a logical address range from a higher-level apparatus, a physical block to be allocated to the logical address range from among the plurality of physical blocks. The memory controller is configured to determine, in the internal process, whether to set a migration destination level (an update frequency level of a migration destination physical block) to a same level as or a different level from a migration source level (an update frequency level of a migration source physical block) based on whether or not an attribute of the migration source physical block satisfies a prescribed condition. A nonvolatile memory device includes: a nonvolatile memory including a plurality of physical blocks; and a memory controller configured to execute an internal process of migrating data between physical blocks. The memory controller is configured to select, based on an update ...more ...less
6
US10171243B2
Publication/Patent Number: US10171243B2
Publication date: 2019-01-01
Application number: 15/612,885
Filing date: 2017-06-02
Abstract: A method begins by a first device generating a self-validating message by creating a master key, using the master key to create a message encryption key, encrypting a message using the message encryption key to produce an encrypted message, encrypting the master key using a public key of a second device to produce an encrypted master key, and including a message authentication code of the first device in the self-validating message. The method continues by the second device receiving and decoding the self-validating message by verifying the message authentication code of the first device, and when the message authentication code of the first device is verified, decrypting the encrypted master key using a private key of the second device to recover the master key, using the master key to create the message encryption key, and decrypting the encrypted message using the message encryption key to recover the message. A method begins by a first device generating a self-validating message by creating a master key, using the master key to create a message encryption key, encrypting a message using the message encryption key to produce an encrypted message, encrypting the master key using a ...more ...less
7
US10176043B2
Publication/Patent Number: US10176043B2
Publication date: 2019-01-08
Application number: 15/314,902
Filing date: 2014-07-01
Abstract: Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure. Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an ...more ...less
8
US10171110B1
Publication/Patent Number: US10171110B1
Publication date: 2019-01-01
Application number: 15/640,724
Filing date: 2017-07-03
Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced. Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload ...more ...less
9
US10171111B2
Publication/Patent Number: US10171111B2
Publication date: 2019-01-01
Application number: 15/249,130
Filing date: 2016-08-26
Inventor: Peake, Andrew G.  
Abstract: A method for execution by a computing device of a dispersed storage network. The method begins by determining whether frequency of access to a set of encoded data slices exceeds a frequently accessed threshold. The method continues, when the frequency of access exceeds the frequently accessed threshold, by determining an access amount indicative of a degree that the frequency of access exceeds the frequently accessed threshold. The method continues by generating a number of additional encoded data slices and storing the number of additional encoded data slices in a number of additional storage units, wherein the set of storage units and the number of additional storage units produce an expanded set of storage units. The method continues by sending a plurality of data access requests to subsets of the expanded set of storage units in a distributed manner to improve processing efficiency of the plurality of data access requests. A method for execution by a computing device of a dispersed storage network. The method begins by determining whether frequency of access to a set of encoded data slices exceeds a frequently accessed threshold. The method continues, when the frequency of access exceeds the ...more ...less
10
US10200156B2
Publication/Patent Number: US10200156B2
Publication date: 2019-02-05
Application number: 15/213,329
Filing date: 2016-07-18
Abstract: A processing module of a computing device alternatingly sends a stream of data to a first or second processing device. When receiving the stream of data, the first processing device performs a first portion of a dispersed storage error encoding function on the received stream of data to produce a plurality of sets of a threshold number of slices and writes the plurality of sets of the threshold number of slices into first memory of a dispersed storage network (DSN). When not receiving the stream of data, the first processing device reads the plurality of sets of the threshold number of slices from the first memory, performs a second portion of the dispersed storage error encoding function using the plurality of sets of the threshold number of slices to produce a plurality of sets of redundancy slices, and writes the plurality of sets of redundancy slices into second DSN memory. A processing module of a computing device alternatingly sends a stream of data to a first or second processing device. When receiving the stream of data, the first processing device performs a first portion of a dispersed storage error encoding function on the received stream of ...more ...less