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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10577908B2
Workflow for determining stresses and/or mechanical properties in anisotropic formations
Publication/Patent Number: US10577908B2 Publication Date: 2020-03-03 Application Number: 15/038,689 Filing Date: 2014-11-21 Inventor: Kisra, Saad   Donald, John Adam   De, Gennaro Vincenzo   Assignee: Schlumberger Technology Corporation   IPC: G06F17/50 Abstract: A method, apparatus, and program product estimate anisotropic properties of an anisotropic formation based at least in part on determinations of a deviation of a wellbore associated with the anisotropic formation and an availability of non-sonic measurement data associated with the anisotropic formation. The determinations are used in the selection of at least one computer-implemented model that in turn may be applied to determine one or more unknown elastic constants for an elastic stiffness matrix. A method, apparatus, and program product estimate anisotropic properties of an anisotropic formation based at least in part on determinations of a deviation of a wellbore associated with the anisotropic formation and an availability of non-sonic measurement data associated with ...More ...Less
2 US10579393B2
Circuit and method of power on initialization for configuration memory of FPGA
Publication/Patent Number: US10579393B2 Publication Date: 2020-03-03 Application Number: 15/026,824 Filing Date: 2015-07-21 Inventor: Yang, Xian   Xue, Qinghua   Assignee: Capital Microelectronics Co., Ltd.   IPC: G06F17/50 Abstract: A circuit and method of power on initialization for a configuration memory of an FPGA. The circuit includes: a decoding circuit, a driving circuit, and a configuration memory, where when 0 is written for the 1st time, the decoding circuit turns on a word line corresponding to an address in the configuration memory, and the driving circuit writes content of the word line into 0; and when 0 is written for the ith time, the decoding circuit turns on at least one word line corresponding to at least one address in the configuration memory, and the driving circuit writes content of each word line in the at least one word line into 0, the number of the at least one address being less than or equal to a sum of addresses that have completed writing of 0 for the previous (i−1)th time. A circuit and method of power on initialization for a configuration memory of an FPGA. The circuit includes: a decoding circuit, a driving circuit, and a configuration memory, where when 0 is written for the 1st time, the decoding circuit turns on a word line corresponding to an ...More ...Less
3 US10579764B2
Co-modeling post-lithography critical dimensions and post-etch critical dimensions with multi-task neural networks
Publication/Patent Number: US10579764B2 Publication Date: 2020-03-03 Application Number: 16/001,435 Filing Date: 2018-06-06 Inventor: Sha, Jing   De, Silva Ekmini A.   Dunn, Derren N.   Assignee: International Business Machines Corporation   IPC: G06F17/50 Abstract: A method is presented for constructing a deep neural network based model to concurrently simulate post-lithography critical dimensions (CDs) and post-etch critical dimensions (CDs) and to improve the modeling accuracy of each process respectively. The method includes generating lithographic aerial images of physical design layout patterns, constructing a multi-task neural network including two output channels, training the multi-task neural network with the training data of the lithographic aerial images, and outputting simulated critical dimension values pertaining to lithography and etch processes. A method is presented for constructing a deep neural network based model to concurrently simulate post-lithography critical dimensions (CDs) and post-etch critical dimensions (CDs) and to improve the modeling accuracy of each process respectively. The method includes generating ...More ...Less
4 US10579750B2
Dynamic execution of predictive models
Publication/Patent Number: US10579750B2 Publication Date: 2020-03-03 Application Number: 15/185,524 Filing Date: 2016-06-17 Inventor: Mcelhinney, Adam   Roberts, Tyler   Horrell, Michael   Nicholas, Brad   Assignee: Uptake Technologies, Inc.   IPC: G06F17/50 Abstract: Disclosed herein are systems, devices, and methods related to assets and predictive models and corresponding workflows that are related to the operation of assets. In particular, examples involve assets configured to receive and locally execute predictive models, locally individualize predictive models, and/or locally execute workflows or portions thereof. Disclosed herein are systems, devices, and methods related to assets and predictive models and corresponding workflows that are related to the operation of assets. In particular, examples involve assets configured to receive and locally execute predictive models, locally ...More ...Less
5 US10580499B2
Read only memory
Publication/Patent Number: US10580499B2 Publication Date: 2020-03-03 Application Number: 15/710,851 Filing Date: 2017-09-21 Inventor: Lu, Hsin-pang   Hsu, Chi-hsiu   Chen, Chung-hao   Mou, Ya-nan   Tsai, Chung-cheng   Assignee: UNITED MICROELECTRONICS CORP.   IPC: G11C16/24 Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact. A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction ...More ...Less
6 US10578543B2
Ranking pipes for maintenance in pipe networks using approximate hydraulic metrics
Publication/Patent Number: US10578543B2 Publication Date: 2020-03-03 Application Number: 15/473,433 Filing Date: 2017-03-29 Inventor: Vasan, Arunchandar   Kaushik, Gollakota Phani Bhargava   Manimaran, Abinaya   Sarangan, Venkatesh   Sivasubramaniam, Anand   Assignee: Tata Consultancy Services Limited   IPC: G06F17/50 Abstract: Conventional systems for monitoring pipe networks are generally not scalable, impractical in the field with uncontrolled environments or rely of static features of pipes that are vary depending on the pipes under consideration. The ideal sensor-ed monitoring systems are not economically viable. Systems and methods of the present disclosure provide an improved data-driven model to rank pipes in the order of burst probabilities, by including dynamic feature values of pipes such as pressure and flow that depends on network structure and operations. The present disclosure enables estimating approximate values for the dynamic features since they are hard to estimate accurately in the absence of a calibrated hydraulic model. The present disclosure also validates the estimated approximate dynamic feature values for the purpose of estimating bursts likelihood vis-a-vis accurate values of the dynamic metrics. Conventional systems for monitoring pipe networks are generally not scalable, impractical in the field with uncontrolled environments or rely of static features of pipes that are vary depending on the pipes under consideration. The ideal sensor-ed monitoring systems are not ...More ...Less
7 US10579705B1
Energy design and rating system for buildings
Publication/Patent Number: US10579705B1 Publication Date: 2020-03-03 Application Number: 15/444,282 Filing Date: 2017-02-27 Inventor: Derickson, Russell G.   Assignee: LGHorizon, LLC   IPC: G01K17/00 Abstract: This document generally describes computer-based technology related to energy design and rating systems for buildings. For example, a computer-based energy design and rating system can provide a fast and accurate method for calculating the energy performance and thermal comfort of residential and light commercial buildings. This document generally describes computer-based technology related to energy design and rating systems for buildings. For example, a computer-based energy design and rating system can provide a fast and accurate method for calculating the energy performance and thermal comfort ...More ...Less
8 US10585659B2
Enabling tenant administrators to initiate request driven peak-hour builds to override off-peak patching schedules
Publication/Patent Number: US10585659B2 Publication Date: 2020-03-10 Application Number: 15/940,835 Filing Date: 2018-03-29 Inventor: Krishnaswamy, Chandramouleeswaran   Nigam, Rahul   Guzman, Eladio   Gilbert, Mark Raymond   Cai, Jianfeng   Dhrolia, Mustafaraj M.   Harwood, Peter Kenneth   Sharma, Esha   Lu, Jay   Isaak, Donovan   Assignee: Microsoft Technology Licensing, LLC   IPC: G06F9/44 Abstract: A system enables initiation of request driven peak-hour builds to override “off-peak” patching schedules for updating server applications. An “off-peak” patching schedule is generated to minimize disruption from installing builds of patches. Notwithstanding the “off-peak” patching schedule, a tenant administrator initiates request driven peak-hour builds when some performance failure occurs during peak business hours. For example, the tenant administrator may generate a service request that includes incident data that is usable to identify and/or develop a particular patch for resolving the performance failure. Based on the service request, the “off-peak” patching schedule is overridden to expedite an out-of-sequence installation of a particular patch. In this way, a tenant administrator that becomes aware that some performance failure is disrupting information workers during a peak usage time-range (e.g., business hours) is empowered to initiate a request driven peak-hour build to quickly resolve the performance failure during the peak usage time-range. A system enables initiation of request driven peak-hour builds to override “off-peak” patching schedules for updating server applications. An “off-peak” patching schedule is generated to minimize disruption from installing builds of patches ...More ...Less
9 US10591638B2
Inversion of geophysical data on computer system having parallel processors
Publication/Patent Number: US10591638B2 Publication Date: 2020-03-17 Application Number: 14/165,326 Filing Date: 2014-01-27 Inventor: Willen, Dennis E.   Jing, Charlie   Assignee: ExxonMobil Upstream Research Company   IPC: G01V7/00 Abstract: A method for efficient use of a computing system of parallel processors to perform inversion of geophysical data, or joint inversion of two or more data types. The method includes assigning at least one control processor to control sequence of operations and reduce load imbalance, assigning a group of one or more processors dedicated to updating one or more model parameters, and assigning another group of one or more processors dedicated to forward modeling simulated data. A method for efficient use of a computing system of parallel processors to perform inversion of geophysical data, or joint inversion of two or more data types. The method includes assigning at least one control processor to control sequence of operations and reduce load ...More ...Less
10 US10638601B2
Apparatus comprising conductive traces configured to transmit differential signals in printed circuit boards
Publication/Patent Number: US10638601B2 Publication Date: 2020-04-28 Application Number: 15/674,776 Filing Date: 2017-08-11 Inventor: Huddar, Vinod Arjun   Laguvaram, Abhishek   Assignee: Seagate Technology LLC   IPC: H05K1/02 Abstract: Systems and methods for routing of conductive traces in a printed circuit board are described. In one embodiment, the method may include routing a first trace in a first layer of a printed circuit board of a solid state drive, routing a second trace in a second layer of the printed circuit board, and routing the first trace and the second trace between a serializer/deserializer (SerDes) of a first controller of the solid state drive and a SerDes of a second controller of the solid state driver. In some cases, the first trace and the second trace may be configured to transmit differential signals to communicate data between the first controller and the second controller. In some embodiments, the second layer may be adjacent to the first layer. Systems and methods for routing of conductive traces in a printed circuit board are described. In one embodiment, the method may include routing a first trace in a first layer of a printed circuit board of a solid state drive, routing a second trace in a second layer of the ...More ...Less
11 US10657305B2
Technique for designing acoustic microwave filters using LCR-based resonator models
Publication/Patent Number: US10657305B2 Publication Date: 2020-05-19 Application Number: 16/400,717 Filing Date: 2019-05-01 Inventor: Raihn, Kurt F.   Turner, Patrick J.   Fenzi, Neal O.   Assignee: Resonant Inc.   IPC: G06F9/455 Abstract: A method for designing a narrowband acoustic wave microwave filter including: generating a modeled filter circuit design having circuit elements including an acoustic resonant element defined by an electrical circuit model that includes a parallel static branch, a parallel motional branch, and one or both of a parallel Bragg Band branch that models an upper Bragg Band discontinuity and a parallel bulk mode function that models an acoustic bulk mode loss; and generating a final circuit design. Generating the final circuit design includes optimizing the modeled filter circuit design to generate an optimized filter circuit design; comparing a frequency response of the optimized filter circuit design to requirements; selecting the optimized filter circuit design for construction into the actual acoustic microwave filter based on the comparison; and transforming the optimized filter circuit design to a design description file for input to a construction process. A method for designing a narrowband acoustic wave microwave filter including: generating a modeled filter circuit design having circuit elements including an acoustic resonant element defined by an electrical circuit model that includes a parallel static branch, a parallel ...More ...Less
12 US10657215B2
Computer implemented system and method for generating a layout of a cell defining a circuit component
Publication/Patent Number: US10657215B2 Publication Date: 2020-05-19 Application Number: 16/253,075 Filing Date: 2019-01-21 Inventor: De, Dood Paul Christopher   Assignee: Arm Limited   IPC: G06F17/50 Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology. For selected grid locations within the grid array, a lookup operation is performed in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location. The layout of the cell is then generated by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry. This provides an automated mechanism for generating cells whose layouts conform to a target process technology. The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout ...More ...Less
13 US10657212B2
Application- or algorithm-specific quantum circuit design
Publication/Patent Number: US10657212B2 Publication Date: 2020-05-19 Application Number: 16/134,673 Filing Date: 2018-09-18 Inventor: Shao, Dongbing   Sandberg, Martin O.   Brink, Markus   Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION   IPC: G06F17/50 Abstract: Techniques for designing application or algorithm specific quantum computing circuits for particular applications or algorithms are presented. A design component can comprise an extractor component that can extract qubit pairs determined to satisfy a defined threshold potential of having to use a direct connection between each other in a quantum circuit design based on analysis of an application or algorithm; and a design management component (DMC) that can determine a circuit design of the quantum circuit to use for the application or algorithm based on analysis of characteristics associated with the qubit pairs. DMC can sort the qubit pairs by weighting schemes and the characteristics, comprising the number of affecting downstream qubits, the number of two-qubit gate operations between qubit pairs, and/or whether a qubit pair affects a measurement. Based on the sorting, DMC selects highest ranking qubit pairs to assign a direct connection. Techniques for designing application or algorithm specific quantum computing circuits for particular applications or algorithms are presented. A design component can comprise an extractor component that can extract qubit pairs determined to satisfy a defined threshold potential ...More ...Less