Country
Full text data for US and EP
Status
Type
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC
No.
Publication Number
Title
Publication/Patent Number Publication/Patent Number
Publication date Publication date
Application number Application number
Filing date Filing date
Inventor Inventor
Assignee Assignee
IPC IPC
1
US10167983B2
Publication/Patent Number: US10167983B2
Publication date: 2019-01-01
Application number: 15/099,354
Filing date: 2016-04-14
Abstract: Methods and systems are provided for a quick connect device. In one example, a connector may include a first visual cue for coupling an outer portion to a middle portion and a second visual cue for coupling an inner portion to the middle portion.
2
US10168133B2
Publication/Patent Number: US10168133B2
Publication date: 2019-01-01
Application number: 14/986,705
Filing date: 2016-01-03
Inventor: Mckendrick, Blair T.  
Abstract: A gauge for checking the tolerance of a manufactured tube having at least one bend therein is digitally manufactured layer-by-layer using an additive manufacturing machine. Multiple features of the gauge are integrated with each other within a common reference coordinate system to precisely locate the features relative to each other. A gauge for checking the tolerance of a manufactured tube having at least one bend therein is digitally manufactured layer-by-layer using an additive manufacturing machine. Multiple features of the gauge are integrated with each other within a common reference coordinate system ...more ...less
3
US10169004B2
Publication/Patent Number: US10169004B2
Publication date: 2019-01-01
Application number: 15/586,991
Filing date: 2017-05-04
Abstract: Embodiments of systems and methods disclosed herein provide an application development platform in an enterprise computing environment. More specifically, in certain embodiments, systems and methods are disclosed that enable an application development platform to reuse, extend, and/or customize entity-based applications in an enterprise computing environment. The application development platform can extend an entity to include user configured settings including zero or at least one of a property, a permission, an action, a behavior, or a resource to the entity to generate user customized versions of the entity. The applications may be customized by an end user, while allowing the underlying application to be updated without losing any user customizations. Embodiments of systems and methods disclosed herein provide an application development platform in an enterprise computing environment. More specifically, in certain embodiments, systems and methods are disclosed that enable an application development platform to reuse, extend ...more ...less
4
US10169496B2
Publication/Patent Number: US10169496B2
Publication date: 2019-01-01
Application number: 14/418,869
Filing date: 2013-09-27
Abstract: A springback amount evaluation method evaluates an amount of springback after die release of a press forming product by a computer and includes: setting a plurality of section planes intersecting a shape of the press forming product at predetermined intervals; obtaining a sectional shape of the press forming product for each of the set section planes; and obtaining an orientation of each of the sectional shapes in each section plane as a direction of the each of the sectional shapes, wherein for each of a shape to be a reference of the press forming product and a shape after the die release, the above-described three steps are performed, and the amount of springback is evaluated by comparing, for all of the section planes, the obtained directions of the sectional shapes for the shape to be the reference and for the shape after the die release. A springback amount evaluation method evaluates an amount of springback after die release of a press forming product by a computer and includes: setting a plurality of section planes intersecting a shape of the press forming product at predetermined intervals; obtaining a ...more ...less
5
US10169510B2
Publication/Patent Number: US10169510B2
Publication date: 2019-01-01
Application number: 15/813,280
Filing date: 2017-11-15
Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data. Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a ...more ...less
6
US10169519B2
Publication/Patent Number: US10169519B2
Publication date: 2019-01-01
Application number: 15/910,730
Filing date: 2018-03-02
Abstract: Respective large block synthesis (LBS) blocks of an integrated circuit (IC) are overlapped along a corner of each respective LBS block to form an overlap area having an area less than respective areas of respective LBS blocks that are overlapped. A first portion of the overlap area is allocated to a first LBS block and configured to be used by the first LBS block, and a second portion of the overlap area is allocated to a second LBS block and configured to be used by the second LBS block. Respective large block synthesis (LBS) blocks of an integrated circuit (IC) are overlapped along a corner of each respective LBS block to form an overlap area having an area less than respective areas of respective LBS blocks that are overlapped. A first portion of the overlap ...more ...less
7
US10169521B2
Publication/Patent Number: US10169521B2
Publication date: 2019-01-01
Application number: 15/479,271
Filing date: 2017-04-04
Abstract: A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two overlapping regions and one contact plug region in between the two overlapping regions in each active region pattern; and (b) forming a contact plug pattern in each contact plug region, the contact plug pattern respectively includes a parallelogram, and an included angle of the parallelogram is not equal to 90°. The contact plug pattern in each active region pattern partially overlaps the two buried gate pattern, respectively. The step (a) to the step (b) are implemented using a computer. A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two ...more ...less
8
US10169522B2
Publication/Patent Number: US10169522B2
Publication date: 2019-01-01
Application number: 14/543,326
Filing date: 2014-11-17
Abstract: The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time. The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography ...more ...less
9
US10175386B2
Publication/Patent Number: US10175386B2
Publication date: 2019-01-08
Application number: 15/061,628
Filing date: 2016-03-04
Inventor: Dogru, Ali H.  
Abstract: A subsurface hydrocarbon reservoir with a horizontal well or multiple vertical wells is simulated by sequential solution of reservoir and well equations to simulate fluid flow inside the reservoir and well production rates. Sequential solution of reservoir and well equations treats wells as specified bottom hole pressure wells. This avoids solving large matrices resulting from the simultaneous solution of the reservoir and well equations which can be computationally very expensive for large number of unknowns and require special sparse matrix solvers. Such sequential solution involves regular reservoir system solvers complemented by small matrices for the numerical solution of the well bottom hole pressures. The solution is performed on tridiagonal matrices for the adjacent reservoir cells to the well cells at the perforated well intervals; and a vector of the unknown reservoir potentials for the adjacent reservoir cells. A subsurface hydrocarbon reservoir with a horizontal well or multiple vertical wells is simulated by sequential solution of reservoir and well equations to simulate fluid flow inside the reservoir and well production rates. Sequential solution of reservoir and well equations ...more ...less
10
US10179030B2
Publication/Patent Number: US10179030B2
Publication date: 2019-01-15
Application number: 13/658,739
Filing date: 2012-10-23
Abstract: Embodiments include a system for determining cardiovascular information for a patient. The system may include at least one computer system configured to receive patient-specific data regarding a geometry of the patient's heart, and create a three-dimensional model representing at least a portion of the patient's heart based on the patient-specific data. The at least one computer system may be further configured to create a physics-based model relating to a blood flow characteristic of the patient's heart and determine a fractional flow reserve within the patient's heart based on the three-dimensional model and the physics-based model. Embodiments include a system for determining cardiovascular information for a patient. The system may include at least one computer system configured to receive patient-specific data regarding a geometry of the patient's heart, and create a three-dimensional model representing ...more ...less
11
US10180457B1
Publication/Patent Number: US10180457B1
Publication date: 2019-01-15
Application number: 15/062,013
Filing date: 2016-03-04
Abstract: The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to process. The method may further include selecting a sliced failing pattern set and generating a plurality of copies of a pattern associated with the sliced failing pattern set, wherein each of the plurality of copies corresponds to one of the plurality of defect locations. The method may also include simulating the plurality of copies of the pattern in parallel. The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include ...more ...less