Country
Full text data for US and EP
Status
Type
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC
No.
Publication Number
Title
Publication/Patent Number Publication/Patent Number
Publication date Publication date
Application number Application number
Filing date Filing date
Inventor Inventor
Assignee Assignee
IPC IPC
1
US10229966B2
Publication/Patent Number: US10229966B2
Publication date: 2019-03-12
Application number: 15/419,002
Filing date: 2017-01-30
Abstract: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure. Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the ...more ...less
2
US10224317B2
Publication/Patent Number: US10224317B2
Publication date: 2019-03-05
Application number: 15/618,684
Filing date: 2017-06-09
Inventor: Kilger, Thomas  
Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads. A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first ...more ...less
3
US10276502B2
Publication/Patent Number: US10276502B2
Publication date: 2019-04-30
Application number: 15/555,381
Filing date: 2015-11-27
Abstract: A method for manufacturing a semiconductor device includes: a process of forming a Cu wiring electrode by a plating method above a semiconductor element using a wide bandgap semiconductor as a base material; a reducing process of reducing the Cu wiring electrode under a NH3 atmosphere; a heating process of heating the Cu wiring electrode at the same time as the reducing process; a process of forming a diffusion prevention film covering the Cu wiring electrode after the heating process; and a sealing process of covering the diffusion prevention film with an organic resin film. A method for manufacturing a semiconductor device includes: a process of forming a Cu wiring electrode by a plating method above a semiconductor element using a wide bandgap semiconductor as a base material; a reducing process of reducing the Cu wiring electrode under a NH3 ...more ...less
4
US10276513B2
Publication/Patent Number: US10276513B2
Publication date: 2019-04-30
Application number: 15/589,195
Filing date: 2017-05-08
Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit. Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In ...more ...less
5
US10170333B2
Publication/Patent Number: US10170333B2
Publication date: 2019-01-01
Application number: 15/947,977
Filing date: 2018-04-09
Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring. Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first ...more ...less
6
US10170415B2
Publication/Patent Number: US10170415B2
Publication date: 2019-01-01
Application number: 15/752,818
Filing date: 2016-07-25
Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform. On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers ...more ...less
7
US10177027B2
Publication/Patent Number: US10177027B2
Publication date: 2019-01-08
Application number: 15/679,914
Filing date: 2017-08-17
Inventor: Wang, Xianchao  
Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a substrate and a multilayer film having a step-shaped portion on the substrate; forming a protective layer covering the step-shaped portion of the multilayer film; forming a capping layer having a plurality of steps on the protective layer covering the semiconductor substrate; and removing at least one layer of the multilayer film to form a cavity that is defined by the capping layer and a remaining multilayer film that has the at least one layer removed. The thus formed semiconductor device does not have cracks in the steps of the capping layer when performing an etch process, thereby improving the performance of the semiconductor device. A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a substrate and a multilayer film having a step-shaped portion on the substrate; forming a protective layer covering the step-shaped portion of the multilayer film; forming a ...more ...less
8
US10319601B2
Publication/Patent Number: US10319601B2
Publication date: 2019-06-11
Application number: 15/467,866
Filing date: 2017-03-23
Abstract: A slurry for chemical mechanical planarization includes water, 1-3 wt. % of abrasive particles having an average diameter of at least 10 nm and less than 100 nm and an outer surface of ceria, and ½-3 wt. % of at least one amine.
9
US10319677B2
Publication/Patent Number: US10319677B2
Publication date: 2019-06-11
Application number: 15/993,042
Filing date: 2018-05-30
Abstract: A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction perpendicular to the surface of the substrate, where the conductive silicide pillar is on the conductive silicide base, and wherein the conductive silicide pillar includes an upper portion having a width, W5, a base having a width, W6, and a neck region having a width, W7, where W7<W5, and W7≤W6. A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction perpendicular to the surface of the substrate, where the conductive silicide pillar is on the conductive silicide base, and ...more ...less
10
US10319805B2
Publication/Patent Number: US10319805B2
Publication date: 2019-06-11
Application number: 15/626,271
Filing date: 2017-06-19
Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole. Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch ...more ...less
11
US10297444B2
Publication/Patent Number: US10297444B2
Publication date: 2019-05-21
Application number: 15/824,143
Filing date: 2017-11-28
Abstract: Methods of producing metal-containing thin films with low impurity contents on a substrate by atomic layer deposition (ALD) are provided. The methods preferably comprise contacting a substrate with alternating and sequential pulses of a metal source chemical, a second source chemical and a deposition enhancing agent. The deposition enhancing agent is preferably selected from the group consisting of hydrocarbons, hydrogen, hydrogen plasma, hydrogen radicals, silanes, germanium compounds, nitrogen compounds, and boron compounds. In some embodiments, the deposition-enhancing agent reacts with halide contaminants in the growing thin film, improving film properties. Methods of producing metal-containing thin films with low impurity contents on a substrate by atomic layer deposition (ALD) are provided. The methods preferably comprise contacting a substrate with alternating and sequential pulses of a metal source chemical, a second source ...more ...less
12
US10373908B2
Publication/Patent Number: US10373908B2
Publication date: 2019-08-06
Application number: 15/850,564
Filing date: 2017-12-21
Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap. A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive ...more ...less
13
US10347591B2
Publication/Patent Number: US10347591B2
Publication date: 2019-07-09
Application number: 15/703,253
Filing date: 2017-09-13
Abstract: A metallic, stress-tunable thin film structure is applied to the backside of an epitaxial wafer to compensate for stress created by the frontside epitaxial layers. The structure may comprise multiple layers, including a metallic stress compensation layer (“SCL”), a metallic adhesive layer and/or a passivation (or solder attach) layer. In other embodiments, the stress compensation structure comprises only the metallic stress compensation layer. In a first application, the metallic stress compensation structure is applied to a backside of an epitaxial wafer prior to beginning device fabrication, correcting for bow present in as-purchased wafers. In a second application, the metallic stress compensation structure is applied to a backside of a thinned epitaxial wafer at the completion of frontside processing, preventing bow-induced wafer breakage upon removal from the rigid support structure or carrier disc. A metallic, stress-tunable thin film structure is applied to the backside of an epitaxial wafer to compensate for stress created by the frontside epitaxial layers. The structure may comprise multiple layers, including a metallic stress compensation layer (“SCL”), a ...more ...less
14
US10354889B2
Publication/Patent Number: US10354889B2
Publication date: 2019-07-16
Application number: 15/651,607
Filing date: 2017-07-17
Abstract: Processing methods may be performed to limit damage of features of a substrate, such as missing fin damage. The methods may include forming a plasma of an inert precursor within a processing region of a processing chamber. Effluents of the plasma of the inert precursor may be utilized to passivate an exposed region of an oxygen-containing material that extends about a feature formed on a semiconductor substrate. A plasma of a hydrogen-containing precursor may also be formed within the processing region. Effluents of the plasma of the hydrogen-containing precursor may be directed, with DC bias, towards an exposed silicon-containing material on the semiconductor substrate. The methods may also include anisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, where the plasma effluents of the hydrogen-containing precursor selectively etch silicon relative to silicon oxide. Processing methods may be performed to limit damage of features of a substrate, such as missing fin damage. The methods may include forming a plasma of an inert precursor within a processing region of a processing chamber. Effluents of the plasma of the inert precursor may be ...more ...less
15
US10332746B1
Publication/Patent Number: US10332746B1
Publication date: 2019-06-25
Application number: 15/920,753
Filing date: 2018-03-14
Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light. Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a ...more ...less