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1
US10170316B2
Publication/Patent Number: US10170316B2
Publication date: 2019-01-01
Application number: 15/722,193
Filing date: 2017-10-02
Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based transistor. A nanosheet stack is formed over a substrate. The nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A tri-layer gate metal stack is formed on each nanosheet. The tri-layer gate metal stack includes an inner nitride layer formed on a surface of each nanosheet, a doped transition metal layer formed on each inner nitride layer, and an outer nitride layer formed on each doped transition metal layer. Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based transistor. A nanosheet stack is formed over a substrate. The nanosheet stack includes a first nanosheet vertically stacked ...more ...less
2
US10170333B2
Publication/Patent Number: US10170333B2
Publication date: 2019-01-01
Application number: 15/947,977
Filing date: 2018-04-09
Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring. Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first ...more ...less
3
US10170415B2
Publication/Patent Number: US10170415B2
Publication date: 2019-01-01
Application number: 15/752,818
Filing date: 2016-07-25
Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform. On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers ...more ...less
4
US10269726B2
Publication/Patent Number: US10269726B2
Publication date: 2019-04-23
Application number: 15/641,568
Filing date: 2017-07-05
Abstract: Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, a first electronic component mounted on a first region of a front surface of the substrate, a mold resin that covers the front surface of the substrate so as to embed the first electronic component therein, and a laminated film covering an upper surface of the mold resin, the laminated film including a magnetic film and a first metal film. The first metal film is connected to the power supply pattern. The magnetic film is selectively thick on the first region. Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, a first electronic component mounted on a first region of a front surface of the substrate, a mold resin that covers the front surface of the substrate so as to embed the first ...more ...less
5
US10269982B2
Publication/Patent Number: US10269982B2
Publication date: 2019-04-23
Application number: 15/205,799
Filing date: 2016-07-08
Abstract: In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer. In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is ...more ...less
6
US20190019750A1
Publication/Patent Number: US20190019750A1
Publication date: 2019-01-17
Application number: 15/788,812
Filing date: 2017-10-20
Abstract: The present invention discloses a polysilicon fuse and fabrication method thereof. The polysilicon fuse comprises a polysilicon fuse-link and two leading terminals, the polysilicon fuse-link comprises a substrate, a first insulating layer and a poly silicon melt. The substrate is formed with a groove, which is covered by the first insulating layer. The polysilicon melt is formed on the first insulating layer and is embedded in the groove. Since the polysilicon melt is embedded in the groove of the substrate, the polysilicon melt is separated away from the nearby devices on the substrate by a sufficient safety distance, which effectively reduce or eliminate the effects of the particles generated during the blowing of the polysilicon melt on the nearby devices. The present invention discloses a polysilicon fuse and fabrication method thereof. The polysilicon fuse comprises a polysilicon fuse-link and two leading terminals, the polysilicon fuse-link comprises a substrate, a first insulating layer and a poly silicon melt. The substrate ...more ...less
7
US20190019751A1
Publication/Patent Number: US20190019751A1
Publication date: 2019-01-17
Application number: 15/978,153
Filing date: 2018-05-13
Abstract: The present invention discloses a polysilicon fuse fabrication method. The polysilicon fuse comprises a polysilicon fuse-link and two leading terminals, the polysilicon fuse-link comprises a substrate, a first insulating layer and a polysilicon melt. The substrate is formed with a groove, which is covered by the first insulating layer. The polysilicon melt is formed on the first insulating layer and is embedded in the groove. Since the polysilicon melt is embedded in the groove of the substrate, the polysilicon melt is separated away from the nearby devices on the substrate by a sufficient safety distance, which effectively reduce or eliminate the effects of the particles generated during the blowing of the polysilicon melt on the nearby devices. The present invention discloses a polysilicon fuse fabrication method. The polysilicon fuse comprises a polysilicon fuse-link and two leading terminals, the polysilicon fuse-link comprises a substrate, a first insulating layer and a polysilicon melt. The substrate is formed with ...more ...less
8
US20190013268A1
Publication/Patent Number: US20190013268A1
Publication date: 2019-01-10
Application number: 16/127,645
Filing date: 2018-09-11
Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates. A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate ...more ...less
9
US20190067148A1
Publication/Patent Number: US20190067148A1
Publication date: 2019-02-28
Application number: 16/173,753
Filing date: 2018-10-29
Abstract: A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam ...more ...less
10
US20190053406A1
Publication/Patent Number: US20190053406A1
Publication date: 2019-02-14
Application number: 16/077,158
Filing date: 2016-11-14
Inventor: Tezuka, Hiroyuki  
Abstract: [Object] To reduce electromagnetic noise with ease in a semiconductor device provided with wiring serving as a source of noise. [Solution] The semiconductor device includes first and second substrates. In this semiconductor device, a plurality of first signal lines are wired in a predetermined direction on the first substrate. In addition, in a semiconductor device on which the plurality of first signal lines are wired in the predetermined direction, a second signal line, which produces a plurality of magnetic fields with mutually different directions in a region between two adjacent signal lines of the plurality of first signal lines, is wired on the second substrate. [Object] To reduce electromagnetic noise with ease in a semiconductor device provided with wiring serving as a source of noise. [Solution] The semiconductor device includes first and second substrates. In this semiconductor device, a plurality of first signal lines are wired in ...more ...less
11
US20190072518A1
Publication/Patent Number: US20190072518A1
Publication date: 2019-03-07
Application number: 16/176,105
Filing date: 2018-10-31
Abstract: A method for forming a nanogap includes forming a knockoff feature on a dielectric layer and forming a trench in the dielectric layer on opposite sides of the knockoff feature. A noble metal is deposited in the trenches and over the knockoff feature. A top surface is polished to level the noble metal in the trenches with a top of the dielectric layer to form electrodes in the trenches and to remove the noble metal from the knockoff feature. A nanochannel is etched into the dielectric layer such that the knockoff feature is positioned within the nanochannel. The knockoff feature is removed to form a nanogap between the electrodes. A method for forming a nanogap includes forming a knockoff feature on a dielectric layer and forming a trench in the dielectric layer on opposite sides of the knockoff feature. A noble metal is deposited in the trenches and over the knockoff feature. A top surface is polished to ...more ...less
12
US20190074364A1
Publication/Patent Number: US20190074364A1
Publication date: 2019-03-07
Application number: 15/693,537
Filing date: 2017-09-01
Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate. A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially ...more ...less
13
US20190067205A1
Publication/Patent Number: US20190067205A1
Publication date: 2019-02-28
Application number: 15/689,967
Filing date: 2017-08-29
Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device. A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the ...more ...less
14
US10229966B2
Publication/Patent Number: US10229966B2
Publication date: 2019-03-12
Application number: 15/419,002
Filing date: 2017-01-30