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1
US20190013253A1
Publication/Patent Number: US20190013253A1
Publication date: 2019-01-10
Application number: 16/131,149
Filing date: 2018-09-14
Abstract: A substrate for chip package and a chip package are provided. A portion on an upper surface of a base material of the substrate that is uncovered by a solder mask is provided with at least one substrate feature point. The upper surface of the base material of the substrate is provided with at least one slot. The slot is configured to guide an irregularly flowing packaging material in the course of chip packaging. The problem of covering the substrate feature point due to irregular flowing of a packaging material is solved with the substrate with no need to re-design a different mold and substrate feature point. A substrate for chip package and a chip package are provided. A portion on an upper surface of a base material of the substrate that is uncovered by a solder mask is provided with at least one substrate feature point. The upper surface of the base material of the substrate is ...more ...less
2
US20190074347A1
Publication/Patent Number: US20190074347A1
Publication date: 2019-03-07
Application number: 16/176,506
Filing date: 2018-10-31
Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.
3
EP3050095B1
Publication/Patent Number: EP3050095B1
Publication date: 2019-02-13
Application number: 13894646.2
Filing date: 2013-09-27
4
EP3448133A1
Publication/Patent Number: EP3448133A1
Publication date: 2019-02-27
Application number: 17786025.1
Filing date: 2017-04-20
Inventor: Onitsuka, Yoshitomo  
Abstract: A multi-piece wiring substrate includes a matrix substrate including a first principal face and a second principal face opposite to the first principal face, the matrix substrate being provided with a plurality of wiring substrate regions, the matrix substrate being provided with dividing grooves arranged along boundaries of the wiring substrate regions in the first principal face and the second principal face, the dividing grooves including first dividing grooves located along respective first sides of the wiring substrate regions in the first principal face, second dividing grooves arranged in the second principal face so as to be opposite to the first dividing grooves, respectively, third dividing grooves located along respective second sides of the wiring substrate regions in the first principal face, and fourth dividing grooves arranged in the second principal face so as to be opposite to the third dividing grooves, respectively, depths of the first dividing grooves and depths of the second dividing grooves being set to be greater than depths of the third dividing grooves and depths of the fourth dividing grooves, first curved parts being provided so that the depths of the third dividing grooves gradually increase as going toward respective corners of the wiring substrate regions, and second curved parts being provided so that the depths of the fourth dividing grooves gradually increase as going toward the respective corners of the wiring substrate regions. A multi-piece wiring substrate includes a matrix substrate including a first principal face and a second principal face opposite to the first principal face, the matrix substrate being provided with a plurality of wiring substrate regions, the matrix substrate being provided ...more ...less
5
EP3474644A1
Publication/Patent Number: EP3474644A1
Publication date: 2019-04-24
Application number: 17813043.1
Filing date: 2017-05-08
Abstract: Provided is a multilayer wiring board for inspection of electronic components which has excellent reliability by improving the adhesiveness between a resin wiring portion and a ceramic wiring substrate. A multilayer wiring board 10 according to the present invention includes: a ceramic wiring substrate 20 having a substrate main surface 21 and a substrate rear surface 22; substrate-side conductive layers 32, 33 formed on the substrate main surface 21; and a resin wiring portion 40 stacked on the substrate main surface 21 so as to cover the substrate-side conductive layers 32, 33. Inspection pads 50, 51 for inspection of electronic components are formed on a front surface 49 of the resin wiring portion 40. End surfaces of the substrate-side conductive layers 33 are exposed from side surfaces 13 of the multilayer wiring board 10. An outer peripheral edge of a rear surface of the resin wiring portion 40 is in contact with the surfaces of the substrate-side conductive layers 33, and end surfaces of the resin wiring portion 40 and the end surfaces of the substrate-side conductive layers 33 are positioned closer to the center of the board than end surfaces 23 of the ceramic wiring substrate 20. Provided is a multilayer wiring board for inspection of electronic components which has excellent reliability by improving the adhesiveness between a resin wiring portion and a ceramic wiring substrate. A multilayer wiring board 10 according to the present invention includes: a ...more ...less
6
EP3471517A1
Publication/Patent Number: EP3471517A1
Publication date: 2019-04-17
Application number: 17810380.0
Filing date: 2017-06-08
Inventor: Kishimoto, Takaomi  
Abstract: A ceramic circuit substrate according to the present invention includes a ceramic substrate, a copper circuit made of a copper-based material bonded, via a bonding layer, to a surface of the ceramic, and a copper heat sink made of the copper-based material bonded, via a bonding layer, to the other surface of the ceramic. The bonding layers each include a brazing material component including two or more kinds of metals, such as Ag, and an active metal having a predetermined concentration. The bonding layers each include a brazing material layer including the brazing material component, and an active metal compound layer containing the active metal. A ratio of a bonding area of the active metal compound layer in a bonding area of each of the bonding layers is 88% or more. A ceramic circuit substrate according to the present invention includes a ceramic substrate, a copper circuit made of a copper-based material bonded, via a bonding layer, to a surface of the ceramic, and a copper heat sink made of the copper-based material bonded, via a bonding ...more ...less
7
US10217701B1
Publication/Patent Number: US10217701B1
Publication date: 2019-02-26
Application number: 15/910,349
Filing date: 2018-03-02
Abstract: A semiconductor device includes a package substrate having a first surface and a second surface. A semiconductor chip is provided on the first surface of the package substrate and includes a semiconductor element. An adhesive is provided between the semiconductor chip and the package substrate. A metal bump is provided on the second surface. A package substrate is a multilayer substrate that includes first to fourth wiring layers and first to third resin layers. CTE1<CTE2<CTE3<CTE4 is satisfied where coefficients of thermal expansion of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are CTE1 to CTE4, respectively. EM1>EM3>EM2>EM4 is satisfied where elastic moduli of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are EM1 to EM4, respectively. A semiconductor device includes a package substrate having a first surface and a second surface. A semiconductor chip is provided on the first surface of the package substrate and includes a semiconductor element. An adhesive is provided between the semiconductor chip and the ...more ...less
8
US10186465B2
Publication/Patent Number: US10186465B2
Publication date: 2019-01-22
Application number: 15/748,138
Filing date: 2015-09-25
Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel. Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first ...more ...less
9
US10192806B2
Publication/Patent Number: US10192806B2
Publication date: 2019-01-29
Application number: 15/180,627
Filing date: 2016-06-13
Abstract: A semiconductor device includes an insulating substrate having a metal plate, an insulating resin plate, and a circuit plate laminated in order; a semiconductor element fixed to the circuit plate; a wiring member connected to an electrode disposed on a front surface of the semiconductor element or to the circuit plate of the insulating substrate; a housing accommodating the insulating substrate, the semiconductor element, and the wiring member; and a sealing material including a thermosetting resin, and sealing the insulating substrate, the semiconductor element, and the wiring member accommodated in the housing. The circuit plate of the insulating substrate is selectively formed on the insulating resin plate as a combination of a circuit pattern with a sealing material adhering pattern. A semiconductor device includes an insulating substrate having a metal plate, an insulating resin plate, and a circuit plate laminated in order; a semiconductor element fixed to the circuit plate; a wiring member connected to an electrode disposed on a front surface of the ...more ...less
10
US10205134B2
Publication/Patent Number: US10205134B2
Publication date: 2019-02-12
Application number: 15/690,943
Filing date: 2017-08-30
Inventor: Zhou, Weifeng  
Abstract: A packaging method and a display device are disclosed. The packaging method includes: packaging a display element on a substrate having the display element disposed thereon to form a package covering the display element, wherein a first substance is disposed on at least a part of the substrate inside the package, the first substance including thermite; and initiating the first substance to obtain a second substance including a product of the thermite reaction. A packaging method and a display device are disclosed. The packaging method includes: packaging a display element on a substrate having the display element disposed thereon to form a package covering the display element, wherein a first substance is disposed on at least a part ...more ...less
11
US10166580B2
Publication/Patent Number: US10166580B2
Publication date: 2019-01-01
Application number: 15/544,690
Filing date: 2016-01-22
Abstract: An aluminum foil includes a first main surface and a second main surface located opposite to the first main surface. In at least one of the first main surface and the second main surface, a surface roughness Ra is not more than 10 nm, a surface roughness Rz is not more than 40 nm in each of a rolling direction and a direction perpendicular to the rolling direction, and the number of peak counts is not less than 10 when a reference length is 40 μm, the number of peak counts being determined from a roughness curve in at least one of the rolling direction and the direction perpendicular to the rolling direction. An aluminum foil includes a first main surface and a second main surface located opposite to the first main surface. In at least one of the first main surface and the second main surface, a surface roughness Ra is not more than 10 nm, a surface roughness Rz is not more than 40 ...more ...less
12
EP2555426B1
Publication/Patent Number: EP2555426B1
Publication date: 2019-01-09
Application number: 11765420.2
Filing date: 2011-03-24
Abstract: A base of a surface-mount electronic component package holds an electronic component element and is to be mounted on a circuit board with a conductive bonding material. The base has a principal surface and an external connection terminal to be electrically connected to the circuit board. The external connection terminal is formed in the principal surface. The base includes a bump formed on the external connection terminal. The bump is smaller than the external connection terminal. The base has a distance d between an outer periphery end edge of the external connection terminal and an outer periphery end edge of the bump along an attenuating direction of stress on the external connection terminal. The stress is generated in association of mounting of the base on the circuit board. The distance d is more than 0.00 mm and equal to or less than 0.45 mm. A base of a surface-mount electronic component package holds an electronic component element and is to be mounted on a circuit board with a conductive bonding material. The base has a principal surface and an external connection terminal to be electrically connected to the ...more ...less
13
US10276422B2
Publication/Patent Number: US10276422B2
Publication date: 2019-04-30
Application number: 15/539,481
Filing date: 2015-12-25
Inventor: Kubota, Satoshi  
Abstract: A semiconductor device substrate and wiring member including a first noble metal plating layer to become internal terminals is formed at predetermined sites on a metal plate, a metal plating layer is formed on the first noble metal plating layer as having a same shape as the first noble metal plating layer, a second noble metal plating layer to become external terminals is formed on a part of the metal plating layer, and a height of a surface of the second noble metal plating layer from a surface of the metal plate is larger than a height of a surface of the first noble metal plating layer from the surface of the metal plate. A semiconductor device substrate and wiring member including a first noble metal plating layer to become internal terminals is formed at predetermined sites on a metal plate, a metal plating layer is formed on the first noble metal plating layer as having a same shape as the ...more ...less
14
US10290605B2
Publication/Patent Number: US10290605B2
Publication date: 2019-05-14
Application number: 15/800,548
Filing date: 2017-11-01
Abstract: Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The passivation layer partially exposes a top surface of the conductive pad. The package structure also includes an encapsulation layer surrounding the semiconductor die. The package structure further includes a dielectric layer covering the semiconductor die and the encapsulation layer. In addition, the package structure includes a redistribution layer covering the dielectric layer. The redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad. Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer ...more ...less
15
US10288676B2
Publication/Patent Number: US10288676B2
Publication date: 2019-05-14
Application number: 15/633,136
Filing date: 2017-06-26
Abstract: A circuit test structure includes: a chip including a conductive line which traces a perimeter of the chip; an interposer electrically connected to the chip; and a Kelvin test structure including: at least three electrical connections to the conductive line; and a testing site. The Kelvin test structure is configured to electrically connect the testing site to the conductive line. A circuit test structure includes: a chip including a conductive line which traces a perimeter of the chip; an interposer electrically connected to the chip; and a Kelvin test structure including: at least three electrical connections to the conductive line; and a testing site ...more ...less
16
US10308560B2
Publication/Patent Number: US10308560B2
Publication date: 2019-06-04
Application number: 15/545,586
Filing date: 2016-01-19
Inventor: Aoki, Katsuyuki  
Abstract: The present invention provides a high thermal conductive silicon nitride sintered body having a thermal conductivity of 50 W/m·K or more and a three-point bending strength of 600 MPa or more, wherein when an arbitrary cross section of the silicon nitride sintered body is subjected to XRD analysis and highest peak intensities detected at diffraction angles of 29.3±0.2°, 29.7±0.2°, 27.0±0.2°, and 36.1±0.2° are expressed as I29.3°, I29.7°, I27.0°, and I36.1°, a peak ratio (I29.3°)/(I27.0°+I36.1°) satisfies a range of 0.01 to 0.08, and a peak ratio (I29.7°)/(I27.0°+I36.1°) satisfies a range of 0.02 to 0.16. Due to above configuration, there can be provided a silicon nitride sintered body having a high thermal conductivity of 50 W/m·K or more, and excellence in insulating properties and strength. The present invention provides a high thermal conductive silicon nitride sintered body having a thermal conductivity of 50 W/m·K or more and a three-point bending strength of 600 MPa or more, wherein when an arbitrary cross section of the silicon nitride sintered body is ...more ...less
17
US20190157177A1
Publication/Patent Number: US20190157177A1
Publication date: 2019-05-23
Application number: 16/140,132
Filing date: 2018-09-24
Inventor: Ichimura, Toru  
Abstract: A semiconductor device includes a printed wiring board; a first semiconductor module including a first package body and a first heat radiation surface on one surface of the first package body, another surface of the first package body, facing the first heat radiation surface, faces one face of the printed wiring board; a first heat radiator on the first heat radiation surface; a second semiconductor module including a second package body and a second heat radiation surface on one surface of the second package body, another surface of the second package body, facing the second heat radiation surface, faces another face of the printed wiring board; and a second heat radiator provided on the second heat radiation surface. The first and second semiconductor modules are arranged to overlap each other in a plan view. The second semiconductor module is connected in parallel to the first semiconductor module. A semiconductor device includes a printed wiring board; a first semiconductor module including a first package body and a first heat radiation surface on one surface of the first package body, another surface of the first package body, facing the first heat radiation surface ...more ...less