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1
US20190051744A1
Publication/Patent Number: US20190051744A1
Publication date: 2019-02-14
Application number: 16/054,524
Filing date: 2018-08-03
Abstract: Fabrication of a microelectronic device comprising a semiconductor structure provided with semiconductor bars positioned above one another, the method comprising the following steps: creating, on a substrate, a stacked structure comprising an alternation of first bars containing a first material and having a first critical dimension and second bars (142, 144, 146) containing a second material, the second material being a semiconductor, the second bars having a second critical dimension greater than the first critical dimension, then, surface doping protruding lateral portions (15) of the second bars before formation of a source and drain block on these portions. Fabrication of a microelectronic device comprising a semiconductor structure provided with semiconductor bars positioned above one another, the method comprising the following steps: creating, on a substrate, a stacked structure comprising an alternation ...more ...less
2
US20190057966A1
Publication/Patent Number: US20190057966A1
Publication date: 2019-02-21
Application number: 15/869,227
Filing date: 2018-01-12
Abstract: A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel region between the source/drain regions; a lightly doped drain (LDD) region between one of the source/drain regions and the channel region; and a gate structure disposed on the channel region. An upper portion of the active region may include an epitaxial growth layer having a larger lattice constant than silicon (Si), and the source/drain regions and the LDD region may be doped with gallium (Ga). A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel region between the source/drain regions; a lightly doped drain (LDD) region between one of the source/drain regions and the ...more ...less
3
US20190067478A1
Publication/Patent Number: US20190067478A1
Publication date: 2019-02-28
Application number: 15/692,471
Filing date: 2017-08-31
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a first fin structure over the base. The semiconductor device structure includes an isolation layer over the base. The first fin structure is partially in the isolation layer. The semiconductor device structure includes a first gate structure over and across the first fin structure. The semiconductor device structure includes a first source structure and a first drain structure on the first fin structure and on two opposite sides of the first gate structure. The first source structure and the first drain structure are made of an N-type conductivity material. The semiconductor device structure includes a cap layer covering the first source structure and the first drain structure. The cap layer is doped with a Group IIIA element. A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a first fin structure over the base. The semiconductor device structure includes an isolation layer over the base. The first fin structure is partially in the ...more ...less
4
US20190067130A1
Publication/Patent Number: US20190067130A1
Publication date: 2019-02-28
Application number: 15/686,698
Filing date: 2017-08-25
Abstract: A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature. A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first ...more ...less
5
US20190006469A1
Publication/Patent Number: US20190006469A1
Publication date: 2019-01-03
Application number: 15/871,374
Filing date: 2018-01-15
Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure. Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure ...more ...less
6
US20190006505A1
Publication/Patent Number: US20190006505A1
Publication date: 2019-01-03
Application number: 15/636,712
Filing date: 2017-06-29
Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs. Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include ...more ...less
7
US20190035941A1
Publication/Patent Number: US20190035941A1
Publication date: 2019-01-31
Application number: 16/149,621
Filing date: 2018-10-02
Inventor: Oh, Dong Yean  
Assignee: SK hynix Inc.
Abstract: In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the nano-wire exposed through the hard mask pattern. The hard mask pattern may be removed. A gate insulating layer may be formed on the nano-wire. A gate may be formed to surround the nano-wire. In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the ...more ...less
8
US20190027583A1
Publication/Patent Number: US20190027583A1
Publication date: 2019-01-24
Application number: 16/000,125
Filing date: 2018-06-05
Abstract: A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA metalorganic dopant precursor. The methods may further include depositing a Group IV semiconductor on a surface of the substrate. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided. A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV ...more ...less
9
US10269652B2
Publication/Patent Number: US10269652B2
Publication date: 2019-04-23
Application number: 15/466,519
Filing date: 2017-03-22
Abstract: An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process. An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low ...more ...less
10
US10269810B2
Publication/Patent Number: US10269810B2
Publication date: 2019-04-23
Application number: 15/790,886
Filing date: 2017-10-23
Inventor: Liaw, Jhon Jhy  
Abstract: A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes. A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the ...more ...less
11
US10269896B2
Publication/Patent Number: US10269896B2
Publication date: 2019-04-23
Application number: 15/587,896
Filing date: 2017-05-05
Abstract: A method of manufacturing semiconductor devices in a semiconductor wafer comprises forming charge compensation device structures in the semiconductor wafer. An electric characteristic related to the charge compensation device structures is measured. At least one of proton irradiation and annealing parameters are adjusted based on the measured electric characteristic. The semiconductor wafer is irradiated with protons and annealed based on the at least one of the adjusted proton irradiation and annealing parameters. Laser beam irradiation parameters are adjusted with respect to different positions on the semiconductor wafer based on the measured electric characteristic. The semiconductor wafer is irradiated with a photon beam at the different positions on the wafer based on the photon beam irradiation parameters. A method of manufacturing semiconductor devices in a semiconductor wafer comprises forming charge compensation device structures in the semiconductor wafer. An electric characteristic related to the charge compensation device structures is measured. At least one of proton ...more ...less
12
US20190109217A1
Publication/Patent Number: US20190109217A1
Publication date: 2019-04-11
Application number: 16/206,464
Filing date: 2018-11-30
Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions. An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the ...more ...less
13
US20190109234A1
Publication/Patent Number: US20190109234A1
Publication date: 2019-04-11
Application number: 16/199,445
Filing date: 2018-11-26
Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3. Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because ...more ...less