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1
EP2975767B1
Publication/Patent Number: EP2975767B1
Publication Date: 2020-01-22
Application Number: 14177479.4
Filing Date: 2014-07-17
Inventor: Strijker, Joan  
Assignee: NXP B.V.
2
US10536139B2
Publication/Patent Number: US10536139B2
Publication Date: 2020-01-14
Application Number: 15/958,768
Filing Date: 2018-04-20
Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short. A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge ...More ...Less
3
US2020021282A1
Publication/Patent Number: US2020021282A1
Publication Date: 2020-01-16
Application Number: 16/503,725
Filing Date: 2019-07-05
Abstract: A gate drive circuit includes a driver for driving a gate of a switching element, a peak voltage detector, and a drive capacity calculator. The peak voltage detector detects a peak voltage at a main terminal of the switching element when the switching element is OFF. The drive capacity calculator calculates a voltage difference value between the detected peak voltage and an allowable voltage value at the main terminal of the switching element, where the allowable voltage is based on the specifications of the switching element. The drive capacity calculator changes a drive capacity of the driver to gradually decrease the difference between the detected peak voltage and the allowable voltage. A gate drive circuit includes a driver for driving a gate of a switching element, a peak voltage detector, and a drive capacity calculator. The peak voltage detector detects a peak voltage at a main terminal of the switching element when the switching element is OFF. The drive ...More ...Less
4
US2020019222A1
Publication/Patent Number: US2020019222A1
Publication Date: 2020-01-16
Application Number: 16/189,284
Filing Date: 2018-11-13
Inventor: Yin, Jen-pei  
Abstract: A power supply device includes a power output terminal, a power converter and an electronic circuit breaker. In view of operation of the electronic circuit breaker, when an electric appliance that acts as a load is connected between the power output terminal and a ground terminal, the electronic circuit breaker is activated to output voltage from the power converter to the power output terminal so as to charge the electric appliance. When the electric appliance is done with charging and is removed, the electronic circuit breaker is deactivated to prevent voltage of the power converter from being outputted to the power output terminal. Thus, even if the power output terminal is exposed, the power output terminal won't output power to result in electric shock because of users' inadvertent contact when no electric appliance is being charged, thereby enhancing operational safety. A power supply device includes a power output terminal, a power converter and an electronic circuit breaker. In view of operation of the electronic circuit breaker, when an electric appliance that acts as a load is connected between the power output terminal and a ground ...More ...Less
5
US10200041B2
Publication/Patent Number: US10200041B2
Publication Date: 2019-02-05
Application Number: 15/340,423
Filing Date: 2016-11-01
Abstract: An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled. An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch ...More ...Less
6
US10256810B2
Publication/Patent Number: US10256810B2
Publication Date: 2019-04-09
Application Number: 15/926,158
Filing Date: 2018-03-20
Inventor: Shirao, Akira  
Abstract: Provided are an electronic circuit and electronic timepiece that can initialize internal circuits even if chattering occurs when a battery is installed. In the electronic circuit, when the initialization state hold signal is input, the initialization control circuit continues outputting the initialization control signal at the first level until the clock signal is output; and when the initialization state hold signal is input and the clock signal is output, outputs the initialization control signal at the second level cancelling the initialization process to the initialization circuit. Provided are an electronic circuit and electronic timepiece that can initialize internal circuits even if chattering occurs when a battery is installed. In the electronic circuit, when the initialization state hold signal is input, the initialization control circuit continues ...More ...Less
7
US10236871B2
Publication/Patent Number: US10236871B2
Publication Date: 2019-03-19
Application Number: 15/795,366
Filing Date: 2017-10-27
Inventor: Chan, On Bon Peter  
Abstract: A pulse width filtering circuit for filtering pulse signals includes an input transition detection circuit detecting change of state of an input signal, including a first transition from a low signal to a high signal and a second transition from the high signal to the low signal; a first delay circuit determining whether the high signal from the first transition is maintained longer than a first period and, if so, generating a first output indicative of the first transition, after the first period; a second delay circuit determining whether the low signal from the second transition is maintained for longer than a second period and, if so, generating a second output indicative of the second transition, after the second period; and a switching circuit connected to the first and second delay circuits and selectively outputting the first output and the second output, based on the state of the input signal. A pulse width filtering circuit for filtering pulse signals includes an input transition detection circuit detecting change of state of an input signal, including a first transition from a low signal to a high signal and a second transition from the high signal to the low ...More ...Less
8
US10250206B2
Publication/Patent Number: US10250206B2
Publication Date: 2019-04-02
Application Number: 15/730,918
Filing Date: 2017-10-12
Inventor: Honda, Kazutaka  
Abstract: A voltage detection circuit includes two detection capacitors, which are paired and configured differentially, first to third detection switches, a drive part, a minimum selector and a maximum selector. The first detection switch is formed of a pMOS transistor, which opens and closes a path between one of the detection capacitors and an input node. The second detection switch is formed of an nMOS transistor, which opens and closes a path between the other of the detection capacitors and an input node. The third detection switch is formed of a series circuit of a pMOS transistor and an nMOS transistor, which open and close a path between two detection capacitors. The driving part turns on and off complementarily between the first and second switches and the third detection switch. The minimum selector applies a lower one of voltages of the input nodes as a substrate potential of the nMOS transistor. The maximum selector applies a higher one of the voltages of the input nodes as a substrate potential of the pMOS transistor. A voltage detection circuit includes two detection capacitors, which are paired and configured differentially, first to third detection switches, a drive part, a minimum selector and a maximum selector. The first detection switch is formed of a pMOS transistor, which opens and ...More ...Less
9
US10250250B2
Publication/Patent Number: US10250250B2
Publication Date: 2019-04-02
Application Number: 15/689,491
Filing Date: 2017-08-29
Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology. The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability ...More ...Less
10
US10306170B2
Publication/Patent Number: US10306170B2
Publication Date: 2019-05-28
Application Number: 15/601,071
Filing Date: 2017-05-22
Inventor: Kim, Tae-gyu  
Assignee: SK hynix Inc.
Abstract: A comparison device includes a comparison block suitable for comparing an upper ramp signal or a lower ramp signal with a pixel signal, and outputting a comparison signal; a CDS block provided between a first input terminal into which the pixel signal is inputted and a negative input terminal of the comparison block, and configured to perform correlated double sampling; a second switch provided between a second input terminal into which the lower ramp signal is inputted and a positive input terminal of the comparison block; a third switch provided between a third input terminal into which the upper ramp signal is inputted and the positive input terminal of the comparison block; and a feedback control unit suitable for checking a magnitude of the pixel signal according the comparison signal and outputting a second control signal or a third control signal for controlling the second or third switch. A comparison device includes a comparison block suitable for comparing an upper ramp signal or a lower ramp signal with a pixel signal, and outputting a comparison signal; a CDS block provided between a first input terminal into which the pixel signal is inputted and a negative ...More ...Less
11
US10204563B2
Publication/Patent Number: US10204563B2
Publication Date: 2019-02-12
Application Number: 14/837,595
Filing Date: 2015-08-27
Abstract: A semiconductor device including a test circuit is miniaturized. The semiconductor device includes r first input terminals (r is an integer of 2 or more), a second input terminal, r functional circuits, a demultiplexer, and a switch circuit. The demultiplexer is a pass transistor logic circuit. R output terminals of the demultiplexer are electrically connected to respective input terminals of the functional circuit and the input terminal is electrically connected to the second input teiminal. Input terminals of the r circuits are electrically connected to the respective first input terminals through the switch circuit. For example, a signal for verification is input to the first input terminal in verification of the functional circuit to operate the demultiplexer. One signal for verification is input to r functional circuits by the demultiplexer. A semiconductor device including a test circuit is miniaturized. The semiconductor device includes r first input terminals (r is an integer of 2 or more), a second input terminal, r functional circuits, a demultiplexer, and a switch circuit. The demultiplexer is a pass ...More ...Less
12
US10333508B2
Publication/Patent Number: US10333508B2
Publication Date: 2019-06-25
Application Number: 15/472,460
Filing Date: 2017-03-29
Abstract: A semiconductor circuit is provided having a crossbar switch arrangement, which includes at least one multiplexer, an output of which corresponds to an output of the crossbar switch arrangement. The arrangement also includes: a set of input lines connected to data inputs of the multiplexer, the input lines extending along a first direction of the semiconductor circuit; and a set of select lines connected to select inputs of the multiplexer, the select lines extending along a second direction of the semiconductor circuit, where the second direction differs from the first direction. The multiplexer includes at least one multiplexing circuit for generating a multiplexed signal from signals present at the input lines and at least one primary output driver for generating an output signal from the multiplexed signal. A semiconductor circuit is provided having a crossbar switch arrangement, which includes at least one multiplexer, an output of which corresponds to an output of the crossbar switch arrangement. The arrangement also includes: a set of input lines connected to data inputs of the ...More ...Less
13
US10432184B1
Publication/Patent Number: US10432184B1
Publication Date: 2019-10-01
Application Number: 16/217,658
Filing Date: 2018-12-12
Abstract: Channel switchover power multiplexer circuits, and methods of operating the same are disclosed. An example power multiplexer a first transistor coupled to a first input, a second transistor coupled to the first transistor to couple a first voltage at the first input to an output, a third transistor coupled to a second input, a fourth transistor coupled to the third transistor to couple a second voltage at the second input to the output, a diode amplifier to provide a third voltage to a gate of the first transistor to block a reverse current, and a soft-start amplifier to provide a fourth voltage to a gate of the fourth transistor to turn on (with adjustable VOUT ramp rate) the fourth transistor with a constant ramp rate. Channel switchover power multiplexer circuits, and methods of operating the same are disclosed. An example power multiplexer a first transistor coupled to a first input, a second transistor coupled to the first transistor to couple a first voltage at the first input to an ...More ...Less