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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10530397B2
Butterfly network on load data return
Publication/Patent Number: US10530397B2 Publication Date: 2020-01-07 Application Number: 15/651,055 Filing Date: 2017-07-17 Inventor: Balasubramanian, Dheera   Zbiciak, Joseph   Bui, Duc Quang   Anderson, Timothy David   Assignee: TEXAS INSTRUMENTS INCORPORATED   IPC: H03M13/00 Abstract: A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each ...More ...Less
2 US10552259B2
Recovery combining hard decoding, soft decoding and artificial codeword generation
Publication/Patent Number: US10552259B2 Publication Date: 2020-02-04 Application Number: 15/922,793 Filing Date: 2018-03-15 Inventor: Jacobvitz, Adam Noah   Kathawala, Gulzar Ahmed   Stoev, Kroum Stanimirov   Wu, Bin   Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.   IPC: H03M13/00 Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform additional NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense. The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords ...More ...Less
3 US10547326B2
Error correction in a flash memory
Publication/Patent Number: US10547326B2 Publication Date: 2020-01-28 Application Number: 15/667,464 Filing Date: 2017-08-02 Inventor: Docquier, Guillaume   Gontara, Ahmed   Assignee: PROTON WORLD INTERNATIONAL N.V.   IPC: H03M13/05 Abstract: A method includes storing data and metadata related to the data in logical words in a non-volatile memory. For each logical word stored in the non-volatile memory, a corresponding error-correction code is generated. Each physical word stored contains a logical word and the corresponding error-correction code. The metadata may contain atomicity information. The non-volatile memory may be a flash memory. Each physical word may contain a parity bit based on the logical word and the corresponding error-correction code stored in the physical word. The logical words may be encoded into physical words including the corresponding error correction code using an encoding table. The data and the metadata may be split into logical words. A method includes storing data and metadata related to the data in logical words in a non-volatile memory. For each logical word stored in the non-volatile memory, a corresponding error-correction code is generated. Each physical word stored contains a logical word and the ...More ...Less
4 US10545826B2
Layered error correction encoding for large scale distributed object storage system
Publication/Patent Number: US10545826B2 Publication Date: 2020-01-28 Application Number: 15/605,906 Filing Date: 2017-05-25 Inventor: Regni, Giorgio   Rancurel, Vianney   Sy, Lam Pham   Assignee: Scality, S.A.   IPC: G06F11/00 Abstract: A method is described. The method includes fragmenting data of an object for storage into an object storage system into multiple data fragments and performing a first error correction encoding process on the data to generate one or more parity fragments for the object. The method also includes sending the multiple data fragments and the one or more parity fragments over a network to different storage servers of the object storage system. The method also includes performing the following at each of the different storage servers: i) incorporating the received one of the multiple data fragments and one or more parity fragments into an extent comprising multiple fragments of other objects; ii) performing a second error correction encoding process on multiple extents including the extent to generate parity information for the multiple extents; and, iii) storing the multiple extents and the parity information. A method is described. The method includes fragmenting data of an object for storage into an object storage system into multiple data fragments and performing a first error correction encoding process on the data to generate one or more parity fragments for the object. The ...More ...Less
5 US10541783B2
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
Publication/Patent Number: US10541783B2 Publication Date: 2020-01-21 Application Number: 16/026,766 Filing Date: 2018-07-03 Inventor: Baek, Jongseob   Back, Seoyoung   Ko, Woosuk   Hong, Sungryong   Assignee: LG ELECTRONICS INC.   IPC: H04B1/04 Abstract: A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data. A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the ...More ...Less
6 US10554225B2
Data storage device encoding and interleaving codewords to improve trellis sequence detection
Publication/Patent Number: US10554225B2 Publication Date: 2020-02-04 Application Number: 16/105,689 Filing Date: 2018-08-20 Inventor: Chen, Yiming   Krishnan, Anantha Raman   Assignee: Western Digital Technologies, Inc.   IPC: H03M13/00 Abstract: A data storage device is disclosed comprising a storage medium. Input data is encoded according to at least one channel code constraint to generate first data and second data. The first data is encoded into a first codeword, and the second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium. A data storage device is disclosed comprising a storage medium. Input data is encoded according to at least one channel code constraint to generate first data and second data. The first data is encoded into a first codeword, and the second data is encoded into a second codeword ...More ...Less
7 US10560120B2
Elementary check node processing for syndrome computation for non-binary LDPC codes decoding
Publication/Patent Number: US10560120B2 Publication Date: 2020-02-11 Application Number: 15/694,062 Filing Date: 2017-09-01 Inventor: Marchand, Cédric   Boutillon, Emmanuel   Assignee: UNIVERSITE DE BRETAGNE SUD   IPC: H03M13/11 Abstract: At least a method and an apparatus are presented to decode a signal encoded using an error correcting code. For example, a decoder comprising a check node processing unit is presented. The check node processing unit is configured to receive at least three input messages and to generate at least one output message. A syndrome calculator is configured to determine a set of syndromes from the at least three input messages using at least two elementary check node processors. A decorrelation unit is configured to determine, in association with at least an output message, a set of candidate components from the set of syndromes. A selection unit is configured to determine at least an output message by selecting components comprising distinct symbols from the set of candidate components associated with the at least an output message. At least a method and an apparatus are presented to decode a signal encoded using an error correcting code. For example, a decoder comprising a check node processing unit is presented. The check node processing unit is configured to receive at least three input messages and to ...More ...Less
8 US10560119B2
Method for performing encoding on basis of parity check matrix of LDPC code in wireless communication system and terminal using same
Publication/Patent Number: US10560119B2 Publication Date: 2020-02-11 Application Number: 16/248,223 Filing Date: 2019-01-15 Inventor: Byun, Ilmu   Kim, Jinwoo   Noh, Kwangseok   Shin, Jongwoong   Kim, Bonghoe   Assignee: LG Electronics Inc.   IPC: H03M13/11 Abstract: A method for performing encoding on the basis of a parity check matrix of a LDPC code, according to one embodiment of the present invention, comprises the steps of: generating, by a terminal, a parity check matrix, wherein the parity check matrix corresponds to a characteristic matrix, each element of the characteristic matrix corresponds to a shift index value determined by a modulo operation between a corresponding element in a base matrix and a lifting value, and the base matrix is a 46×68 matrix; and performing, by the terminal, encoding of input data by using the parity check matrix, wherein the lifting value is associated with the length of the input data. A method for performing encoding on the basis of a parity check matrix of a LDPC code, according to one embodiment of the present invention, comprises the steps of: generating, by a terminal, a parity check matrix, wherein the parity check matrix corresponds to a characteristic ...More ...Less
9 US10567010B2
Flexible polar encoders and decoders
Publication/Patent Number: US10567010B2 Publication Date: 2020-02-18 Application Number: 16/213,452 Filing Date: 2018-12-07 Inventor: Gross, Warren   Sarkis, Gabi   Giard, Pascal   Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY   IPC: H03M13/00 Abstract: Methods and systems for encoding data are described herein. The method comprises inputting data to a first pipeline of a non-systematic polar encoder capable of encoding a polar code of length nmax, extracting, via at least one first multiplexer of size log nmax×1, a first polar code of length n<nmax at a first location along the first pipeline to generate a first encoded output, modifying the first encoded output to set frozen bits to a known value to obtain a modified first encoded output, inputting the modified first encoded output to a second pipeline of the non-systematic polar encoder, and extracting, via at least one second multiplexer of size log nmax×1, a second polar code of length n<nmax at a second location along the second pipeline to generate a second encoded output, the second encoded output corresponding to a systematically encoded polar code of length n. Methods and systems for encoding data are described herein. The method comprises inputting data to a first pipeline of a non-systematic polar encoder capable of encoding a polar code of length nmax, extracting, via at least one first multiplexer of size log nmax×1, a first ...More ...Less
10 US10572189B2
Method and decoder to adjust an error locator polynomial based on an error parity
Publication/Patent Number: US10572189B2 Publication Date: 2020-02-25 Application Number: 15/343,866 Filing Date: 2016-11-04 Inventor: Ilani, Ishai   Assignee: SANDISK TECHNOLOGIES LLC   IPC: G06F11/10 Abstract: A method of operation of a decoder includes receiving first data at the decoder. The method further includes generating second data at the decoder based on the first data. The second data is generated by adjusting an error locator polynomial based on an error parity of the first data. A method of operation of a decoder includes receiving first data at the decoder. The method further includes generating second data at the decoder based on the first data. The second data is generated by adjusting an error locator polynomial based on an error parity of the first ...More ...Less