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1
US10211852B2
Publication/Patent Number: US10211852B2
Publication date: 2019-02-19
Application number: 15/199,222
Filing date: 2016-06-30
Abstract: A CRC calculation method and apparatus are provided. According to technical solutions provided in embodiments of the present invention, a binary sequence of a first pulse includes the first packet and the second packet. The number of bits in the first packet is unequal to the number of bits in the second packet. The first packet is distributed to a first CRC calculation circuit. The second packet is distributed to a second CRC calculation circuit. CRC of the first packet is obtained by calculation by using the first CRC calculation circuit. CRC of the second packet is obtained by using the second CRC calculation circuit. If the foregoing technical solutions are applied to the foregoing application scenario of flexible Ethernet, CRC of packets with different lengths and from different transmitters may be separately calculated. Therefore, the foregoing technical solutions may be better applied to the scenario of flexible Ethernet. A CRC calculation method and apparatus are provided. According to technical solutions provided in embodiments of the present invention, a binary sequence of a first pulse includes the first packet and the second packet. The number of bits in the first packet is unequal to the ...more ...less
2
US10216671B2
Publication/Patent Number: US10216671B2
Publication date: 2019-02-26
Application number: 15/444,273
Filing date: 2017-02-27
Inventor: Shirlen, Martyn  
Abstract: Systems and methods for operating a bus interface unit include queues for receiving and storing one or more words from one or more agents for transmission on to a data bus. From at least a subset of the one or more words, a next word which will cause the least switching power among the subset of the one or more words when transmitted on to the data bus is determined and the next word is selected for transmission on to the data bus, to reduce dynamic power consumption of the data bus. The next word may be selected as a word among the subset of the one or more words with a least Hamming distance from a current word scheduled for transmission on to the data bus. Systems and methods for operating a bus interface unit include queues for receiving and storing one or more words from one or more agents for transmission on to a data bus. From at least a subset of the one or more words, a next word which will cause the least switching power ...more ...less
3
US10216436B2
Publication/Patent Number: US10216436B2
Publication date: 2019-02-26
Application number: 15/398,517
Filing date: 2017-01-04
Abstract: A method includes receiving a data access request for a set of encoded data slices. The data access request identifies a new vault in the dispersed storage network (DSN), where the new vault is a logical storage container supported by storage units of the DSN, and where the new vault is defined by vault parameters that include new vault identifier, new vault storage capabilities, access privileges, and authorized users. The method further includes sending an inquiry to the storage units regarding status of the new vault. When a threshold number of storage units provide a status response of active, a computing device sends a set of access requests regarding the data access request to the storage units. When the threshold number of storage units do not provide the status response of active, the computing device facilitates activation of the new vault in at least the threshold number of storage units. A method includes receiving a data access request for a set of encoded data slices. The data access request identifies a new vault in the dispersed storage network (DSN), where the new vault is a logical storage container supported by storage units of the DSN, and where the new ...more ...less
4
US10216443B2
Publication/Patent Number: US10216443B2
Publication date: 2019-02-26
Application number: 15/340,017
Filing date: 2016-11-01
Inventor: Hegde, Harsha  
Abstract: A method for execution by one or more processing modules of a dispersed storage network (DSN), the method begins when accessing a multi-site DSN, by determining, for each site, whether the site is able to favorably support slice access. Unfavorable conditions include any of: weather-related site availability information that is greater than a weather threshold level, seismic activity at the site is greater than a seismic threshold level, general environmental conditions at the site are unfavorable, building fire conditions, unauthorized site physical access conditions, power supply conditions, or network connectivity conditions. The method continues, for each site that is able to favorably support slice access, by selecting one or more storage units to support the accessing. The method continues by issuing access requests to the selected one or more storage units and receiving access responses from at least a threshold number of the selected one or more storage units. A method for execution by one or more processing modules of a dispersed storage network (DSN), the method begins when accessing a multi-site DSN, by determining, for each site, whether the site is able to favorably support slice access. Unfavorable conditions include any of: ...more ...less
5
US10187088B2
Publication/Patent Number: US10187088B2
Publication date: 2019-01-22
Application number: 14/689,870
Filing date: 2015-04-17
Abstract: An apparatus or method for minimizing the total accessing cost, such as minimizing repair bandwidth, delay or the number of hops including the steps of minimizing the number of nodes to be engaged for the recovery process using a polynomial-time solution that determines the optimal number of participating nodes and the optimal set of nodes to be engaged for recovering lost data, where in a distributed database storage system, for example a dynamic system, where the accessing cost or even the number of available nodes are subject to change results in different values for the optimal number of participating nodes. An MDS code is included which can be reused when the number of participating nodes varies without having to change the entire code structure and the content of the nodes. An apparatus or method for minimizing the total accessing cost, such as minimizing repair bandwidth, delay or the number of hops including the steps of minimizing the number of nodes to be engaged for the recovery process using a polynomial-time solution that determines the ...more ...less
6
US10177789B2
Publication/Patent Number: US10177789B2
Publication date: 2019-01-08
Application number: 14/780,303
Filing date: 2014-03-27
Abstract: A receiver receives a signal including an interleaved symbol stream. The receiver includes a convolutional deinterleaver including a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector inputs the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream. A receiver receives a signal including an interleaved symbol stream. The receiver includes a convolutional deinterleaver including a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount ...more ...less
7
US10200061B2
Publication/Patent Number: US10200061B2
Publication date: 2019-02-05
Application number: 16/118,655
Filing date: 2018-08-31
Abstract: An apparatus and a method. The apparatus includes a plurality of polarization processors, including n inputs and n outputs, where n is an integer, wherein the plurality of polarization processors is configured to polarize channels with different bit-channel reliability; and at least one permutation processor, including n inputs and n outputs, wherein each of the at least one permutation processor is connected between two of the plurality of polarization processors, and connects the n outputs of a first of the two of the plurality of polarizations processors to the n inputs of a second of the two of the plurality of polarization processors between which each of the at least one permutation processor is connected in a permutation pattern, wherein at least one permutation processor is configured to not further polarize a bit channel. An apparatus and a method. The apparatus includes a plurality of polarization processors, including n inputs and n outputs, where n is an integer, wherein the plurality of polarization processors is configured to polarize channels with different bit-channel reliability; and at ...more ...less
8
US10200063B2
Publication/Patent Number: US10200063B2
Publication date: 2019-02-05
Application number: 15/599,576
Filing date: 2017-05-19
Abstract: An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the LLR, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the LLR is a LLR of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell. An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using ...more ...less
9
US10200065B2
Publication/Patent Number: US10200065B2
Publication date: 2019-02-05
Application number: 13/975,621
Filing date: 2013-08-26
Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence. An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a ...more ...less
10
US10204007B2
Publication/Patent Number: US10204007B2
Publication date: 2019-02-12
Application number: 14/994,001
Filing date: 2016-01-12
Abstract: The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods may include a soft information correction circuit that is operable to receive soft information corresponding to information accessed from a block of memory cells, and modify the soft information based upon a variance of the soft information and a median of the soft information to create corrected soft information, the corrected soft information being used to mitigate inter-cell interference in the block of memory cells. The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods may include a soft information correction circuit that ...more ...less
11
US10171848B2
Publication/Patent Number: US10171848B2
Publication date: 2019-01-01
Application number: 15/261,415
Filing date: 2016-09-09
Abstract: According to one embodiment, a method of processing broadcast data in a broadcast transmitter includes: encoding the broadcast data for broadcast service; encoding signaling information for signaling the broadcast data; assigning the encoded broadcast data and the encoded signaling information into a signal frame; and transmitting a broadcast signal including the signal frame. The broadcast signal further includes a signaling table having access information of the broadcast data. The signaling table includes service id information for identifying the broadcast service and component information for indicating a number of components in the broadcast service. According to one embodiment, a method of processing broadcast data in a broadcast transmitter includes: encoding the broadcast data for broadcast service; encoding signaling information for signaling the broadcast data; assigning the encoded broadcast data and the encoded ...more ...less
12
US10176040B2
Publication/Patent Number: US10176040B2
Publication date: 2019-01-08
Application number: 15/091,112
Filing date: 2016-04-05
Inventor: Kreifels, Gerard A.  
Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1. The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first ...more ...less
13
US10168904B2
Publication/Patent Number: US10168904B2
Publication date: 2019-01-01
Application number: 15/457,408
Filing date: 2017-03-13
Abstract: Methods for use in a dispersed storage network (DSN) to retrieve encoded data from memory device of an impaired storage unit. In various examples, a computing device of the DSN issues requests to a plurality of storage units, including the impaired storage unit, to recover at least a decode threshold number of encoded data slices of a set of encoded data slices. When the impaired storage unit determines that it is not able to quickly retrieve the requested data slice for provision to the computing device, the impaired storage unit promptly issues a quasi-error response instead. When the computing device receives less than the decode threshold number of encoded data slices and a quasi-error response, it may elect to issue another slice request(s) to another storage unit(s) and/or issue a continue request instructing the impaired storage unit to continue processing the request to recover the data slice stored therein. Methods for use in a dispersed storage network (DSN) to retrieve encoded data from memory device of an impaired storage unit. In various examples, a computing device of the DSN issues requests to a plurality of storage units, including the impaired storage unit, to recover at ...more ...less
14
US10169148B2
Publication/Patent Number: US10169148B2
Publication date: 2019-01-01
Application number: 15/240,591
Filing date: 2016-08-18
Inventor: Resch, Jason K.  
Abstract: A method of apportioning storage units in a dispersed storage network (DSN) includes generating storage unit apportioning data indicating a mapping of a plurality of desired numbers of storage units to a plurality of storage sites based on site reliability data. The mapping includes a first desired number of storage units corresponding to a first one of the plurality of storage sites that is greater than a second desired number of storage units corresponding to a second one of the plurality of storage sites in response to the site reliability data indicating that a first reliability score corresponding to the first one of the plurality of storage sites is more favorable than a second reliability score corresponding to the second one of the plurality of storage sites. A plurality of storage units are allocated to the plurality of storage sites based on the storage unit apportioning data. A method of apportioning storage units in a dispersed storage network (DSN) includes generating storage unit apportioning data indicating a mapping of a plurality of desired numbers of storage units to a plurality of storage sites based on site reliability data. The mapping ...more ...less
15
US10230352B2
Publication/Patent Number: US10230352B2
Publication date: 2019-03-12
Application number: 15/786,500
Filing date: 2017-10-17
Inventor: Zhao, Xudong  
Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power. Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to ...more ...less